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target/arm: ensure we use current exception state after SCR update

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A write to the SCR can change the effective EL by droppping the system
from secure to non-secure mode. However if we use a cached current_el
from before the change we'll rebuild the flags incorrectly. To fix
this we introduce the ARM_CP_NEWEL CP flag to indicate the new EL
should be used when recomputing the flags.

Backports partof commit f80741d107673f162e3b097fc76a1590036cc9d1 from
qemu
This commit is contained in:
Alex Bennée 2020-01-14 07:51:02 -05:00 committed by Lioncash
parent 81c14bb595
commit 639c5c4fe2
2 changed files with 7 additions and 3 deletions
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8
qemu/target/arm/cpu.h
View file

@ -2174,6 +2174,9 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
* RAISES_EXC is for when the read or write hook might raise an exception; * RAISES_EXC is for when the read or write hook might raise an exception;
* the generated code will synchronize the CPU state before calling the hook * the generated code will synchronize the CPU state before calling the hook
* so that it is safe for the hook to call raise_exception(). * so that it is safe for the hook to call raise_exception().
* NEWEL is for writes to registers that might change the exception
* level - typically on older ARM chips. For those cases we need to
* re-read the new el when recomputing the translation flags.
*/ */
#define ARM_CP_SPECIAL 0x0001 #define ARM_CP_SPECIAL 0x0001
#define ARM_CP_CONST 0x0002 #define ARM_CP_CONST 0x0002
@ -2193,10 +2196,11 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
#define ARM_CP_SVE 0x2000 #define ARM_CP_SVE 0x2000
#define ARM_CP_NO_GDB 0x4000 #define ARM_CP_NO_GDB 0x4000
#define ARM_CP_RAISES_EXC 0x8000 #define ARM_CP_RAISES_EXC 0x8000
#define ARM_CP_NEWEL 0x10000
/* Used only as a terminator for ARMCPRegInfo lists */ /* Used only as a terminator for ARMCPRegInfo lists */
#define ARM_CP_SENTINEL 0xffff #define ARM_CP_SENTINEL 0xfffff
/* Mask of only the flag bits in a type field */ /* Mask of only the flag bits in a type field */
#define ARM_CP_FLAG_MASK 0xf0ff #define ARM_CP_FLAG_MASK 0x1f0ff
/* Valid values for ARMCPRegInfo state field, indicating which of /* Valid values for ARMCPRegInfo state field, indicating which of
* the AArch32 and AArch64 execution states this register is visible in. * the AArch32 and AArch64 execution states this register is visible in.

2
qemu/target/arm/helper.c
View file

@ -4933,7 +4933,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
.resetvalue = 0, .writefn = scr_write }, .resetvalue = 0, .writefn = scr_write },
{ .name = "SCR", .type = ARM_CP_ALIAS, { .name = "SCR", .type = ARM_CP_ALIAS | ARM_CP_NEWEL,
.cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
.access = PL1_RW, .accessfn = access_trap_aa32s_el1, .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
.fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),