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target-i386: Create gen_lea_v_seg

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Add forgotten zero-extension in the TARGET_X86_64, !CODE64, ss32 case;
use this new function to implement gen_string_movl_A0_EDI,
gen_string_movl_A0_ESI, gen_add_A0_ds_seg.

Backports commit ca2f29f555805d07fb0b9ebfbbfc4e3656530977 from qemu
This commit is contained in:
Richard Henderson 2018-02-20 09:13:33 -05:00 committed by Lioncash
parent c658126845
commit 63c4e79870
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 59 additions and 127 deletions
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186
qemu/target-i386/translate.c
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@ -497,28 +497,6 @@ static inline void gen_op_add_reg_T0(TCGContext *s, TCGMemOp size, int reg)
gen_op_mov_reg_v(s, size, reg, cpu_tmp0); gen_op_mov_reg_v(s, size, reg, cpu_tmp0);
} }
static inline void gen_op_addl_A0_reg_sN(TCGContext *s, int shift, int reg)
{
TCGv cpu_A0 = *(TCGv *)s->cpu_A0;
TCGv cpu_tmp0 = *(TCGv *)s->cpu_tmp0;
TCGv **cpu_regs = (TCGv **)s->cpu_regs;
tcg_gen_mov_tl(s, cpu_tmp0, *cpu_regs[reg]);
if (shift != 0)
tcg_gen_shli_tl(s, cpu_tmp0, cpu_tmp0, shift);
tcg_gen_add_tl(s, cpu_A0, cpu_A0, cpu_tmp0);
/* For x86_64, this sets the higher half of register to zero.
For i386, this is equivalent to a nop. */
tcg_gen_ext32u_tl(s, cpu_A0, cpu_A0);
}
static inline void gen_op_movl_A0_seg(TCGContext *s, int reg)
{
TCGv cpu_A0 = *(TCGv *)s->cpu_A0;
tcg_gen_ld32u_tl(s, cpu_A0, s->cpu_env, offsetof(CPUX86State, segs[reg].base) + REG_L_OFFSET);
}
static inline void gen_op_addl_A0_seg(DisasContext *s, int reg) static inline void gen_op_addl_A0_seg(DisasContext *s, int reg)
{ {
TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGContext *tcg_ctx = s->uc->tcg_ctx;
@ -526,57 +504,15 @@ static inline void gen_op_addl_A0_seg(DisasContext *s, int reg)
TCGv cpu_tmp0 = *(TCGv *)tcg_ctx->cpu_tmp0; TCGv cpu_tmp0 = *(TCGv *)tcg_ctx->cpu_tmp0;
tcg_gen_ld_tl(tcg_ctx, cpu_tmp0, tcg_ctx->cpu_env, offsetof(CPUX86State, segs[reg].base)); tcg_gen_ld_tl(tcg_ctx, cpu_tmp0, tcg_ctx->cpu_env, offsetof(CPUX86State, segs[reg].base));
#ifdef TARGET_X86_64
if (CODE64(s)) { if (CODE64(s)) {
tcg_gen_andi_tl(tcg_ctx, cpu_A0, cpu_A0, 0xffffffff); tcg_gen_ext32u_tl(tcg_ctx, cpu_A0, cpu_A0);
tcg_gen_add_tl(tcg_ctx, cpu_A0, cpu_A0, cpu_tmp0); tcg_gen_add_tl(tcg_ctx, cpu_A0, cpu_A0, cpu_tmp0);
} else { } else {
tcg_gen_add_tl(tcg_ctx, cpu_A0, cpu_A0, cpu_tmp0); tcg_gen_add_tl(tcg_ctx, cpu_A0, cpu_A0, cpu_tmp0);
tcg_gen_andi_tl(tcg_ctx, cpu_A0, cpu_A0, 0xffffffff); tcg_gen_ext32u_tl(tcg_ctx, cpu_A0, cpu_A0);
} }
#else
tcg_gen_add_tl(tcg_ctx, cpu_A0, cpu_A0, cpu_tmp0);
#endif
} }
#ifdef TARGET_X86_64
static inline void gen_op_movq_A0_seg(TCGContext *s, int reg)
{
TCGv cpu_A0 = *(TCGv *)s->cpu_A0;
tcg_gen_ld_tl(s, cpu_A0, s->cpu_env, offsetof(CPUX86State, segs[reg].base));
}
static inline void gen_op_addq_A0_seg(TCGContext *s, int reg)
{
TCGv cpu_A0 = *(TCGv *)s->cpu_A0;
TCGv cpu_tmp0 = *(TCGv *)s->cpu_tmp0;
tcg_gen_ld_tl(s, cpu_tmp0, s->cpu_env, offsetof(CPUX86State, segs[reg].base));
tcg_gen_add_tl(s, cpu_A0, cpu_A0, cpu_tmp0);
}
static inline void gen_op_movq_A0_reg(TCGContext *s, int reg)
{
TCGv cpu_A0 = *(TCGv *)s->cpu_A0;
TCGv **cpu_regs = (TCGv **)s->cpu_regs;
tcg_gen_mov_tl(s, cpu_A0, *cpu_regs[reg]);
}
static inline void gen_op_addq_A0_reg_sN(TCGContext *s, int shift, int reg)
{
TCGv cpu_A0 = *(TCGv *)s->cpu_A0;
TCGv cpu_tmp0 = *(TCGv *)s->cpu_tmp0;
TCGv **cpu_regs = (TCGv **)s->cpu_regs;
tcg_gen_mov_tl(s, cpu_tmp0, *cpu_regs[reg]);
if (shift != 0)
tcg_gen_shli_tl(s, cpu_tmp0, cpu_tmp0, shift);
tcg_gen_add_tl(s, cpu_A0, cpu_A0, cpu_tmp0);
}
#endif
static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0) static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
{ {
if (HOOK_EXISTS(s->uc, UC_HOOK_MEM_READ)) if (HOOK_EXISTS(s->uc, UC_HOOK_MEM_READ))
@ -613,75 +549,84 @@ static inline void gen_jmp_im(DisasContext *s, target_ulong pc)
gen_op_jmp_v(tcg_ctx, cpu_tmp0); gen_op_jmp_v(tcg_ctx, cpu_tmp0);
} }
static inline void gen_string_movl_A0_ESI(DisasContext *s) /* Compute SEG:REG into A0. SEG is selected from the override segment
(OVR_SEG) and the default segment (DEF_SEG). OVR_SEG may be -1 to
indicate no override. */
static void gen_lea_v_seg(DisasContext *s, TCGv a0, int def_seg, int ovr_seg)
{ {
int override; TCGMemOp aflag = s->aflag;
TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv cpu_A0 = *(TCGv *)tcg_ctx->cpu_A0; TCGv cpu_A0 = *(TCGv *)tcg_ctx->cpu_A0;
TCGv **cpu_regs = (TCGv **)tcg_ctx->cpu_regs;
override = s->override; switch (aflag) {
switch (s->aflag) {
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
case MO_64: case MO_64:
if (override >= 0) { if (ovr_seg < 0) {
gen_op_movq_A0_seg(tcg_ctx, override); tcg_gen_mov_tl(tcg_ctx, cpu_A0, a0);
gen_op_addq_A0_reg_sN(tcg_ctx, 0, R_ESI); return;
} else {
gen_op_movq_A0_reg(tcg_ctx, R_ESI);
} }
break; break;
#endif #endif
case MO_32: case MO_32:
/* 32 bit address */ /* 32 bit address */
if (s->addseg && override < 0) if (ovr_seg < 0) {
override = R_DS; if (s->addseg) {
if (override >= 0) { ovr_seg = def_seg;
gen_op_movl_A0_seg(tcg_ctx, override); } else {
gen_op_addl_A0_reg_sN(tcg_ctx, 0, R_ESI); tcg_gen_ext32u_tl(tcg_ctx, cpu_A0, a0);
} else { return;
gen_op_movl_A0_reg(tcg_ctx, R_ESI); }
} }
break; break;
case MO_16: case MO_16:
/* 16 address, always override */ /* 16 bit address */
if (override < 0) if (ovr_seg < 0) {
override = R_DS; ovr_seg = def_seg;
tcg_gen_ext16u_tl(tcg_ctx, cpu_A0, *cpu_regs[R_ESI]); }
gen_op_addl_A0_seg(s, override); tcg_gen_ext16u_tl(tcg_ctx, cpu_A0, a0);
/* ADDSEG will only be false in 16-bit mode for LEA. */
if (!s->addseg) {
return;
}
a0 = cpu_A0;
break; break;
default: default:
tcg_abort(); tcg_abort();
} }
if (ovr_seg >= 0) {
TCGv seg = tcg_temp_new(tcg_ctx);
tcg_gen_ld_tl(tcg_ctx, seg, tcg_ctx->cpu_env, offsetof(CPUX86State, segs[ovr_seg].base));
if (aflag == MO_64) {
tcg_gen_add_tl(tcg_ctx, cpu_A0, a0, seg);
} else if (CODE64(s)) {
tcg_gen_ext32u_tl(tcg_ctx, cpu_A0, a0);
tcg_gen_add_tl(tcg_ctx, cpu_A0, cpu_A0, seg);
} else {
tcg_gen_add_tl(tcg_ctx, cpu_A0, a0, seg);
tcg_gen_ext32u_tl(tcg_ctx, cpu_A0, cpu_A0);
}
tcg_temp_free(tcg_ctx, seg);
}
}
static inline void gen_string_movl_A0_ESI(DisasContext *s)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv **cpu_regs = (TCGv **)tcg_ctx->cpu_regs;
gen_lea_v_seg(s, *cpu_regs[R_ESI], R_DS, s->override);
} }
static inline void gen_string_movl_A0_EDI(DisasContext *s) static inline void gen_string_movl_A0_EDI(DisasContext *s)
{ {
TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv cpu_A0 = *(TCGv *)tcg_ctx->cpu_A0;
TCGv **cpu_regs = (TCGv **)tcg_ctx->cpu_regs; TCGv **cpu_regs = (TCGv **)tcg_ctx->cpu_regs;
switch (s->aflag) { gen_lea_v_seg(s, *cpu_regs[R_EDI], R_ES, -1);
#ifdef TARGET_X86_64
case MO_64:
gen_op_movq_A0_reg(tcg_ctx, R_EDI);
break;
#endif
case MO_32:
if (s->addseg) {
gen_op_movl_A0_seg(tcg_ctx, R_ES);
gen_op_addl_A0_reg_sN(tcg_ctx, 0, R_EDI);
} else {
gen_op_movl_A0_reg(tcg_ctx, R_EDI);
}
break;
case MO_16:
tcg_gen_ext16u_tl(tcg_ctx, cpu_A0, *cpu_regs[R_EDI]);
gen_op_addl_A0_seg(s, R_ES);
break;
default:
tcg_abort();
}
} }
static inline void gen_op_movl_T0_Dshift(TCGContext *s, TCGMemOp ot) static inline void gen_op_movl_T0_Dshift(TCGContext *s, TCGMemOp ot)
@ -2394,23 +2339,10 @@ static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm)
/* used for LEA and MOV AX, mem */ /* used for LEA and MOV AX, mem */
static void gen_add_A0_ds_seg(DisasContext *s) static void gen_add_A0_ds_seg(DisasContext *s)
{ {
int override, must_add_seg; TCGContext *tcg_ctx = s->uc->tcg_ctx;
must_add_seg = s->addseg; TCGv cpu_A0 = *(TCGv *)tcg_ctx->cpu_A0;
override = R_DS;
if (s->override >= 0) { gen_lea_v_seg(s, cpu_A0, R_DS, s->override);
override = s->override;
must_add_seg = 1;
}
if (must_add_seg) {
#ifdef TARGET_X86_64
if (CODE64(s)) {
gen_op_addq_A0_seg(s->uc->tcg_ctx, override);
} else
#endif
{
gen_op_addl_A0_seg(s, override);
}
}
} }
/* generate modrm memory load or store of 'reg'. TMP0 is used if reg == /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==