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target/riscv: Set htval and mtval2 on execptions

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Backports commit 3067553993ae986b76a92df8a978778134ecdc84 from qemu
This commit is contained in:
Alistair Francis 2020-03-22 02:13:05 -04:00 committed by Lioncash
parent 141c47a286
commit 63d5b37ebc
1 changed files with 9 additions and 0 deletions
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9
qemu/target/riscv/cpu_helper.c
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@ -828,6 +828,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
target_ulong deleg = async ? env->mideleg : env->medeleg; target_ulong deleg = async ? env->mideleg : env->medeleg;
target_ulong tval = 0; target_ulong tval = 0;
target_ulong htval = 0;
target_ulong mtval2 = 0;
if (!async) { if (!async) {
/* set tval to badaddr for traps with address information */ /* set tval to badaddr for traps with address information */
@ -894,6 +896,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
env->hstatus = set_field(env->hstatus, HSTATUS_SPV, env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
riscv_cpu_virt_enabled(env)); riscv_cpu_virt_enabled(env));
htval = env->guest_phys_fault_addr;
riscv_cpu_set_virt_enabled(env, 0); riscv_cpu_set_virt_enabled(env, 0);
riscv_cpu_set_force_hs_excep(env, 0); riscv_cpu_set_force_hs_excep(env, 0);
} else { } else {
@ -904,6 +908,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
get_field(env->mstatus, SSTATUS_SPP)); get_field(env->mstatus, SSTATUS_SPP));
env->hstatus = set_field(env->hstatus, HSTATUS_SPV, env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
riscv_cpu_virt_enabled(env)); riscv_cpu_virt_enabled(env));
htval = env->guest_phys_fault_addr;
} }
} }
@ -916,6 +921,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
env->sepc = env->pc; env->sepc = env->pc;
env->sbadaddr = tval; env->sbadaddr = tval;
env->htval = htval;
env->pc = (env->stvec >> 2 << 2) + env->pc = (env->stvec >> 2 << 2) +
((async && (env->stvec & 3) == 1) ? cause * 4 : 0); ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
riscv_cpu_set_mode(env, PRV_S); riscv_cpu_set_mode(env, PRV_S);
@ -930,6 +936,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
env->mstatus = set_field(env->mstatus, MSTATUS_MTL, env->mstatus = set_field(env->mstatus, MSTATUS_MTL,
riscv_cpu_force_hs_excep_enabled(env)); riscv_cpu_force_hs_excep_enabled(env));
mtval2 = env->guest_phys_fault_addr;
/* Trapping to M mode, virt is disabled */ /* Trapping to M mode, virt is disabled */
riscv_cpu_set_virt_enabled(env, 0); riscv_cpu_set_virt_enabled(env, 0);
riscv_cpu_set_force_hs_excep(env, 0); riscv_cpu_set_force_hs_excep(env, 0);
@ -944,6 +952,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
env->mcause = cause | ~(((target_ulong)-1) >> async); env->mcause = cause | ~(((target_ulong)-1) >> async);
env->mepc = env->pc; env->mepc = env->pc;
env->mbadaddr = tval; env->mbadaddr = tval;
env->mtval2 = mtval2;
env->pc = (env->mtvec >> 2 << 2) + env->pc = (env->mtvec >> 2 << 2) +
((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
riscv_cpu_set_mode(env, PRV_M); riscv_cpu_set_mode(env, PRV_M);