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tcg: Add generic vector expanders

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Backports commit db432672dc50ed86dda17ac821b7eb07411a90af from qemu
This commit is contained in:
Richard Henderson 2018-03-06 12:19:54 -05:00 committed by Lioncash
parent 12fb906688
commit 64365612bf
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
50 changed files with 3100 additions and 19 deletions
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5
msvc/unicorn/aarch64-softmmu/aarch64-softmmu.vcxproj
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@ -37,6 +37,8 @@
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11
msvc/unicorn/aarch64-softmmu/aarch64-softmmu.vcxproj.filters
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@ -72,6 +72,12 @@
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5
msvc/unicorn/aarch64eb-softmmu/aarch64eb-softmmu.vcxproj
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@ -37,6 +37,8 @@
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11
msvc/unicorn/aarch64eb-softmmu/aarch64eb-softmmu.vcxproj.filters
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5
msvc/unicorn/arm-softmmu/arm-softmmu.vcxproj
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@ -36,6 +36,8 @@
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11
msvc/unicorn/arm-softmmu/arm-softmmu.vcxproj.filters
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5
msvc/unicorn/armeb-softmmu/armeb-softmmu.vcxproj
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@ -36,6 +36,8 @@
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11
msvc/unicorn/armeb-softmmu/armeb-softmmu.vcxproj.filters
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5
msvc/unicorn/m68k-softmmu/m68k-softmmu.vcxproj
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@ -26,6 +26,8 @@
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11
msvc/unicorn/m68k-softmmu/m68k-softmmu.vcxproj.filters
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5
msvc/unicorn/mips-softmmu/mips-softmmu.vcxproj
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11
msvc/unicorn/mips-softmmu/mips-softmmu.vcxproj.filters
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5
msvc/unicorn/mips64-softmmu/mips64-softmmu.vcxproj
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msvc/unicorn/mips64-softmmu/mips64-softmmu.vcxproj.filters
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msvc/unicorn/mips64el-softmmu/mips64el-softmmu.vcxproj
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<ClCompile Include="..\..\..\qemu\cputlb.c" />
<ClCompile Include="..\..\..\qemu\exec.c" />
<ClCompile Include="..\..\..\qemu\tcg-runtime.c" />
<ClCompile Include="..\..\..\qemu\tcg-runtime-gvec.c" />
<ClCompile Include="..\..\..\qemu\ioport.c" />
<ClCompile Include="..\..\..\qemu\memory.c" />
<ClCompile Include="..\..\..\qemu\memory_mapping.c" />
@ -90,6 +98,9 @@
<ClCompile Include="..\..\..\qemu\tcg\tcg.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-gvec.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c">
<Filter>tcg</Filter>
</ClCompile>

5
msvc/unicorn/mipsel-softmmu/mipsel-softmmu.vcxproj
View file

@ -31,6 +31,8 @@
<ClInclude Include="..\..\..\qemu\tcg\tcg-op.h" />
<ClInclude Include="..\..\..\qemu\tcg\tcg-opc.h" />
<ClInclude Include="..\..\..\qemu\tcg\tcg-runtime.h" />
<ClInclude Include="..\..\..\qemu\tcg\tcg-op-gvec.h" />
<ClInclude Include="..\..\..\qemu\tcg\tcg-gvec-desc.h" />
<ClInclude Include="..\..\..\qemu\tcg\tcg.h" />
<ClInclude Include="..\..\..\qemu\mipsel.h" />
<ClInclude Include="..\config-host.h" />
@ -43,6 +45,8 @@
<ClCompile Include="..\..\..\qemu\cpus.c" />
<ClCompile Include="..\..\..\qemu\cputlb.c" />
<ClCompile Include="..\..\..\qemu\exec.c" />
<ClCompile Include="..\..\..\qemu\tcg-runtime.c" />
<ClCompile Include="..\..\..\qemu\tcg-runtime-gvec.c" />
<ClCompile Include="..\..\..\qemu\fpu\softfloat.c" />
<ClCompile Include="..\..\..\qemu\hw\mips\addr.c" />
<ClCompile Include="..\..\..\qemu\hw\mips\mips_r4k.c" />
@ -72,6 +76,7 @@
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\optimize.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-gvec.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-common.c" />
<ClCompile Include="..\..\..\qemu\translate-all.c" />

11
msvc/unicorn/mipsel-softmmu/mipsel-softmmu.vcxproj.filters
View file

@ -39,6 +39,12 @@
<ClInclude Include="..\..\..\qemu\tcg\tcg-opc.h">
<Filter>tcg</Filter>
</ClInclude>
<ClInclude Include="..\..\..\qemu\tcg\tcg-gvec-desc.h">
<Filter>tcg</Filter>
</ClInclude>
<ClInclude Include="..\..\..\qemu\tcg\tcg-op-gvec.h">
<Filter>tcg</Filter>
</ClInclude>
<ClInclude Include="..\..\..\qemu\tcg\tcg-runtime.h">
<Filter>tcg</Filter>
</ClInclude>
@ -70,6 +76,8 @@
<ClCompile Include="..\..\..\qemu\cpus.c" />
<ClCompile Include="..\..\..\qemu\cputlb.c" />
<ClCompile Include="..\..\..\qemu\exec.c" />
<ClCompile Include="..\..\..\qemu\tcg-runtime.c" />
<ClCompile Include="..\..\..\qemu\tcg-runtime-gvec.c" />
<ClCompile Include="..\..\..\qemu\ioport.c" />
<ClCompile Include="..\..\..\qemu\memory.c" />
<ClCompile Include="..\..\..\qemu\memory_mapping.c" />
@ -88,6 +96,9 @@
<ClCompile Include="..\..\..\qemu\tcg\tcg.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-gvec.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c">
<Filter>tcg</Filter>
</ClCompile>

5
msvc/unicorn/sparc-softmmu/sparc-softmmu.vcxproj
View file

@ -26,6 +26,8 @@
<ClInclude Include="..\..\..\qemu\tcg\tcg-op.h" />
<ClInclude Include="..\..\..\qemu\tcg\tcg-opc.h" />
<ClInclude Include="..\..\..\qemu\tcg\tcg-runtime.h" />
<ClInclude Include="..\..\..\qemu\tcg\tcg-op-gvec.h" />
<ClInclude Include="..\..\..\qemu\tcg\tcg-gvec-desc.h" />
<ClInclude Include="..\..\..\qemu\tcg\tcg.h" />
<ClInclude Include="..\..\..\qemu\target\sparc\cpu-qom.h" />
<ClInclude Include="..\..\..\qemu\target\sparc\cpu.h" />
@ -43,6 +45,8 @@
<ClCompile Include="..\..\..\qemu\cpus.c" />
<ClCompile Include="..\..\..\qemu\cputlb.c" />
<ClCompile Include="..\..\..\qemu\exec.c" />
<ClCompile Include="..\..\..\qemu\tcg-runtime.c" />
<ClCompile Include="..\..\..\qemu\tcg-runtime-gvec.c" />
<ClCompile Include="..\..\..\qemu\fpu\softfloat.c" />
<ClCompile Include="..\..\..\qemu\hw\sparc\leon3.c" />
<ClCompile Include="..\..\..\qemu\ioport.c" />
@ -66,6 +70,7 @@
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\optimize.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-gvec.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-common.c" />
<ClCompile Include="..\..\..\qemu\translate-all.c" />

11
msvc/unicorn/sparc-softmmu/sparc-softmmu.vcxproj.filters
View file

@ -36,6 +36,12 @@
<ClInclude Include="..\..\..\qemu\tcg\tcg-opc.h">
<Filter>tcg</Filter>
</ClInclude>
<ClInclude Include="..\..\..\qemu\tcg\tcg-gvec-desc.h">
<Filter>tcg</Filter>
</ClInclude>
<ClInclude Include="..\..\..\qemu\tcg\tcg-op-gvec.h">
<Filter>tcg</Filter>
</ClInclude>
<ClInclude Include="..\..\..\qemu\tcg\tcg-runtime.h">
<Filter>tcg</Filter>
</ClInclude>
@ -74,6 +80,9 @@
<ClCompile Include="..\..\..\qemu\tcg\tcg.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-gvec.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c">
<Filter>tcg</Filter>
</ClCompile>
@ -88,6 +97,8 @@
<ClCompile Include="..\..\..\qemu\cpus.c" />
<ClCompile Include="..\..\..\qemu\cputlb.c" />
<ClCompile Include="..\..\..\qemu\exec.c" />
<ClCompile Include="..\..\..\qemu\tcg-runtime.c" />
<ClCompile Include="..\..\..\qemu\tcg-runtime-gvec.c" />
<ClCompile Include="..\..\..\qemu\ioport.c" />
<ClCompile Include="..\..\..\qemu\memory.c" />
<ClCompile Include="..\..\..\qemu\memory_mapping.c" />

5
msvc/unicorn/sparc64-softmmu/sparc64-softmmu.vcxproj
View file

@ -26,6 +26,8 @@
<ClInclude Include="..\..\..\qemu\tcg\tcg-op.h" />
<ClInclude Include="..\..\..\qemu\tcg\tcg-opc.h" />
<ClInclude Include="..\..\..\qemu\tcg\tcg-runtime.h" />
<ClInclude Include="..\..\..\qemu\tcg\tcg-op-gvec.h" />
<ClInclude Include="..\..\..\qemu\tcg\tcg-gvec-desc.h" />
<ClInclude Include="..\..\..\qemu\tcg\tcg.h" />
<ClInclude Include="..\..\..\qemu\target\sparc\cpu-qom.h" />
<ClInclude Include="..\..\..\qemu\target\sparc\cpu.h" />
@ -43,6 +45,8 @@
<ClCompile Include="..\..\..\qemu\cpus.c" />
<ClCompile Include="..\..\..\qemu\cputlb.c" />
<ClCompile Include="..\..\..\qemu\exec.c" />
<ClCompile Include="..\..\..\qemu\tcg-runtime.c" />
<ClCompile Include="..\..\..\qemu\tcg-runtime-gvec.c" />
<ClCompile Include="..\..\..\qemu\fpu\softfloat.c" />
<ClCompile Include="..\..\..\qemu\hw\sparc64\sun4u.c" />
<ClCompile Include="..\..\..\qemu\ioport.c" />
@ -67,6 +71,7 @@
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\optimize.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-gvec.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-common.c" />
<ClCompile Include="..\..\..\qemu\translate-all.c" />

11
msvc/unicorn/sparc64-softmmu/sparc64-softmmu.vcxproj.filters
View file

@ -36,6 +36,12 @@
<ClInclude Include="..\..\..\qemu\tcg\tcg-opc.h">
<Filter>tcg</Filter>
</ClInclude>
<ClInclude Include="..\..\..\qemu\tcg\tcg-gvec-desc.h">
<Filter>tcg</Filter>
</ClInclude>
<ClInclude Include="..\..\..\qemu\tcg\tcg-op-gvec.h">
<Filter>tcg</Filter>
</ClInclude>
<ClInclude Include="..\..\..\qemu\tcg\tcg-runtime.h">
<Filter>tcg</Filter>
</ClInclude>
@ -107,6 +113,9 @@
<ClCompile Include="..\..\..\qemu\tcg\tcg.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-gvec.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c">
<Filter>tcg</Filter>
</ClCompile>
@ -122,6 +131,8 @@
<ClCompile Include="..\..\..\qemu\memory.c" />
<ClCompile Include="..\..\..\qemu\ioport.c" />
<ClCompile Include="..\..\..\qemu\exec.c" />
<ClCompile Include="..\..\..\qemu\tcg-runtime.c" />
<ClCompile Include="..\..\..\qemu\tcg-runtime-gvec.c" />
<ClCompile Include="..\..\..\qemu\cputlb.c" />
<ClCompile Include="..\..\..\qemu\cpus.c" />
<ClCompile Include="..\..\..\qemu\cpu-exec.c" />

5
msvc/unicorn/x86_64-softmmu/x86_64-softmmu.vcxproj
View file

@ -36,6 +36,8 @@
<ClInclude Include="..\..\..\qemu\tcg\tcg-op.h" />
<ClInclude Include="..\..\..\qemu\tcg\tcg-opc.h" />
<ClInclude Include="..\..\..\qemu\tcg\tcg-runtime.h" />
<ClInclude Include="..\..\..\qemu\tcg\tcg-op-gvec.h" />
<ClInclude Include="..\..\..\qemu\tcg\tcg-gvec-desc.h" />
<ClInclude Include="..\..\..\qemu\tcg\tcg.h" />
<ClInclude Include="..\..\..\qemu\x86_64.h" />
<ClInclude Include="..\config-host.h" />
@ -48,6 +50,8 @@
<ClCompile Include="..\..\..\qemu\cpus.c" />
<ClCompile Include="..\..\..\qemu\cputlb.c" />
<ClCompile Include="..\..\..\qemu\exec.c" />
<ClCompile Include="..\..\..\qemu\tcg-runtime.c" />
<ClCompile Include="..\..\..\qemu\tcg-runtime-gvec.c" />
<ClCompile Include="..\..\..\qemu\fpu\softfloat.c" />
<ClCompile Include="..\..\..\qemu\hw\i386\pc.c" />
<ClCompile Include="..\..\..\qemu\hw\i386\pc_piix.c" />
@ -80,6 +84,7 @@
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\optimize.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-gvec.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-common.c" />
<ClCompile Include="..\..\..\qemu\translate-all.c" />

11
msvc/unicorn/x86_64-softmmu/x86_64-softmmu.vcxproj.filters
View file

@ -36,6 +36,12 @@
<ClInclude Include="..\..\..\qemu\tcg\tcg-opc.h">
<Filter>tcg</Filter>
</ClInclude>
<ClInclude Include="..\..\..\qemu\tcg\tcg-gvec-desc.h">
<Filter>tcg</Filter>
</ClInclude>
<ClInclude Include="..\..\..\qemu\tcg\tcg-op-gvec.h">
<Filter>tcg</Filter>
</ClInclude>
<ClInclude Include="..\..\..\qemu\tcg\tcg-runtime.h">
<Filter>tcg</Filter>
</ClInclude>
@ -88,6 +94,8 @@
<ClCompile Include="..\..\..\qemu\cpus.c" />
<ClCompile Include="..\..\..\qemu\cputlb.c" />
<ClCompile Include="..\..\..\qemu\exec.c" />
<ClCompile Include="..\..\..\qemu\tcg-runtime.c" />
<ClCompile Include="..\..\..\qemu\tcg-runtime-gvec.c" />
<ClCompile Include="..\..\..\qemu\ioport.c" />
<ClCompile Include="..\..\..\qemu\memory.c" />
<ClCompile Include="..\..\..\qemu\memory_mapping.c" />
@ -159,6 +167,9 @@
<ClCompile Include="..\..\..\qemu\tcg\tcg.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-gvec.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c">
<Filter>tcg</Filter>
</ClCompile>

4
qemu/Makefile.target
View file

@ -43,11 +43,11 @@ all: $(PROGS)
obj-y = exec.o translate-all.o cpu-exec.o
obj-y += translate-common.o
obj-y += cpu-exec-common.o
obj-$(CONFIG_TCG) += tcg/tcg.o tcg/tcg-op.o tcg/tcg-op-vec.o
obj-$(CONFIG_TCG) += tcg/tcg.o tcg/tcg-op.o tcg/tcg-op-vec.o tcg/tcg-op-gvec.o
obj-$(CONFIG_TCG) += tcg/tcg-common.o tcg/optimize.o
obj-y += fpu/softfloat.o
obj-y += target/$(TARGET_BASE_ARCH)/
obj-y += tcg-runtime.o
obj-y += tcg-runtime.o tcg-runtime-gvec.o
obj-y += accel/
#########################################################

63
qemu/aarch64.h
View file

@ -401,6 +401,7 @@
#define dummy_c15_cp_reginfo dummy_c15_cp_reginfo_aarch64
#define dummy_func dummy_func_aarch64
#define dummy_section dummy_section_aarch64
#define dup_const_impl dup_const_impl_aarch64
#define end_list end_list_aarch64
#define ensure_writable_pages ensure_writable_pages_aarch64
#define eq128 eq128_aarch64
@ -1608,6 +1609,29 @@
#define helper_get_cp_reg64 helper_get_cp_reg64_aarch64
#define helper_get_r13_banked helper_get_r13_banked_aarch64
#define helper_get_user_reg helper_get_user_reg_aarch64
#define helper_gvec_add8 helper_gvec_add8_aarch64
#define helper_gvec_add16 helper_gvec_add16_aarch64
#define helper_gvec_add32 helper_gvec_add32_aarch64
#define helper_gvec_add64 helper_gvec_add64_aarch64
#define helper_gvec_and helper_gvec_and_aarch64
#define helper_gvec_andc helper_gvec_andc_aarch64
#define helper_gvec_dup8 helper_gvec_dup8_aarch64
#define helper_gvec_dup16 helper_gvec_dup16_aarch64
#define helper_gvec_dup32 helper_gvec_dup32_aarch64
#define helper_gvec_dup64 helper_gvec_dup64_aarch64
#define helper_gvec_mov helper_gvec_mov_aarch64
#define helper_gvec_neg8 helper_gvec_neg8_aarch64
#define helper_gvec_neg16 helper_gvec_neg16_aarch64
#define helper_gvec_neg32 helper_gvec_neg32_aarch64
#define helper_gvec_neg64 helper_gvec_neg64_aarch64
#define helper_gvec_not helper_gvec_not_aarch64
#define helper_gvec_or helper_gvec_or_aarch64
#define helper_gvec_orc helper_gvec_orc_aarch64
#define helper_gvec_sub8 helper_gvec_sub8_aarch64
#define helper_gvec_sub16 helper_gvec_sub16_aarch64
#define helper_gvec_sub32 helper_gvec_sub32_aarch64
#define helper_gvec_sub64 helper_gvec_sub64_aarch64
#define helper_gvec_xor helper_gvec_xor_aarch64
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_aarch64
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_aarch64
#define helper_iwmmxt_addcw helper_iwmmxt_addcw_aarch64
@ -2830,6 +2854,7 @@
#define shifter_out_im shifter_out_im_aarch64
#define shortShift128Left shortShift128Left_aarch64
#define shortShift192Left shortShift192Left_aarch64
#define simd_desc simd_desc_aarch64
#define simple_mpu_ap_bits simple_mpu_ap_bits_aarch64
#define size_code_gen_buffer size_code_gen_buffer_aarch64
#define softmmu_lock_user softmmu_lock_user_aarch64
@ -2985,6 +3010,7 @@
#define tcg_enabled tcg_enabled_aarch64
#define tcg_exec_all tcg_exec_all_aarch64
#define tcg_exec_init tcg_exec_init_aarch64
#define tcg_expand_vec_op tcg_expand_vec_op_aarch64
#define tcg_find_helper tcg_find_helper_aarch64
#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_aarch64
#define tcg_func_start tcg_func_start_aarch64
@ -3062,6 +3088,7 @@
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_aarch64
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_aarch64
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_aarch64
#define tcg_gen_dupi_vec tcg_gen_dupi_vec_aarch64
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_aarch64
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_aarch64
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_aarch64
@ -3086,6 +3113,33 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_aarch64
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_aarch64
#define tcg_gen_goto_tb tcg_gen_goto_tb_aarch64
#define tcg_gen_gvec_2 tcg_gen_gvec_2_aarch64
#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_aarch64
#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_aarch64
#define tcg_gen_gvec_3 tcg_gen_gvec_3_aarch64
#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_aarch64
#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_aarch64
#define tcg_gen_gvec_4 tcg_gen_gvec_4_aarch64
#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_aarch64
#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_aarch64
#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_aarch64
#define tcg_gen_gvec_add tcg_gen_gvec_add_aarch64
#define tcg_gen_gvec_and tcg_gen_gvec_and_aarch64
#define tcg_gen_gvec_andc tcg_gen_gvec_andc_aarch64
#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_aarch64
#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_aarch64
#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_aarch64
#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_aarch64
#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_aarch64
#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_aarch64
#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_aarch64
#define tcg_gen_gvec_mov tcg_gen_gvec_mov_aarch64
#define tcg_gen_gvec_neg tcg_gen_gvec_neg_aarch64
#define tcg_gen_gvec_not tcg_gen_gvec_not_aarch64
#define tcg_gen_gvec_or tcg_gen_gvec_or_aarch64
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_aarch64
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_aarch64
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_aarch64
#define tcg_gen_insn_start tcg_gen_insn_start_aarch64
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_aarch64
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_aarch64
@ -3205,6 +3259,15 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_aarch64
#define tcg_gen_subi_i32 tcg_gen_subi_i32_aarch64
#define tcg_gen_subi_i64 tcg_gen_subi_i64_aarch64
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_aarch64
#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_aarch64
#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_aarch64
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_aarch64
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_aarch64
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_aarch64
#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_aarch64
#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_aarch64
#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_aarch64
#define tcg_gen_xor_i32 tcg_gen_xor_i32_aarch64
#define tcg_gen_xor_i64 tcg_gen_xor_i64_aarch64
#define tcg_gen_xor_vec tcg_gen_xor_vec_aarch64

63
qemu/aarch64eb.h
View file

@ -401,6 +401,7 @@
#define dummy_c15_cp_reginfo dummy_c15_cp_reginfo_aarch64eb
#define dummy_func dummy_func_aarch64eb
#define dummy_section dummy_section_aarch64eb
#define dup_const_impl dup_const_impl_aarch64eb
#define end_list end_list_aarch64eb
#define ensure_writable_pages ensure_writable_pages_aarch64eb
#define eq128 eq128_aarch64eb
@ -1608,6 +1609,29 @@
#define helper_get_cp_reg64 helper_get_cp_reg64_aarch64eb
#define helper_get_r13_banked helper_get_r13_banked_aarch64eb
#define helper_get_user_reg helper_get_user_reg_aarch64eb
#define helper_gvec_add8 helper_gvec_add8_aarch64eb
#define helper_gvec_add16 helper_gvec_add16_aarch64eb
#define helper_gvec_add32 helper_gvec_add32_aarch64eb
#define helper_gvec_add64 helper_gvec_add64_aarch64eb
#define helper_gvec_and helper_gvec_and_aarch64eb
#define helper_gvec_andc helper_gvec_andc_aarch64eb
#define helper_gvec_dup8 helper_gvec_dup8_aarch64eb
#define helper_gvec_dup16 helper_gvec_dup16_aarch64eb
#define helper_gvec_dup32 helper_gvec_dup32_aarch64eb
#define helper_gvec_dup64 helper_gvec_dup64_aarch64eb
#define helper_gvec_mov helper_gvec_mov_aarch64eb
#define helper_gvec_neg8 helper_gvec_neg8_aarch64eb
#define helper_gvec_neg16 helper_gvec_neg16_aarch64eb
#define helper_gvec_neg32 helper_gvec_neg32_aarch64eb
#define helper_gvec_neg64 helper_gvec_neg64_aarch64eb
#define helper_gvec_not helper_gvec_not_aarch64eb
#define helper_gvec_or helper_gvec_or_aarch64eb
#define helper_gvec_orc helper_gvec_orc_aarch64eb
#define helper_gvec_sub8 helper_gvec_sub8_aarch64eb
#define helper_gvec_sub16 helper_gvec_sub16_aarch64eb
#define helper_gvec_sub32 helper_gvec_sub32_aarch64eb
#define helper_gvec_sub64 helper_gvec_sub64_aarch64eb
#define helper_gvec_xor helper_gvec_xor_aarch64eb
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_aarch64eb
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_aarch64eb
#define helper_iwmmxt_addcw helper_iwmmxt_addcw_aarch64eb
@ -2830,6 +2854,7 @@
#define shifter_out_im shifter_out_im_aarch64eb
#define shortShift128Left shortShift128Left_aarch64eb
#define shortShift192Left shortShift192Left_aarch64eb
#define simd_desc simd_desc_aarch64eb
#define simple_mpu_ap_bits simple_mpu_ap_bits_aarch64eb
#define size_code_gen_buffer size_code_gen_buffer_aarch64eb
#define softmmu_lock_user softmmu_lock_user_aarch64eb
@ -2985,6 +3010,7 @@
#define tcg_enabled tcg_enabled_aarch64eb
#define tcg_exec_all tcg_exec_all_aarch64eb
#define tcg_exec_init tcg_exec_init_aarch64eb
#define tcg_expand_vec_op tcg_expand_vec_op_aarch64eb
#define tcg_find_helper tcg_find_helper_aarch64eb
#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_aarch64eb
#define tcg_func_start tcg_func_start_aarch64eb
@ -3062,6 +3088,7 @@
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_aarch64eb
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_aarch64eb
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_aarch64eb
#define tcg_gen_dupi_vec tcg_gen_dupi_vec_aarch64eb
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_aarch64eb
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_aarch64eb
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_aarch64eb
@ -3086,6 +3113,33 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_aarch64eb
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_aarch64eb
#define tcg_gen_goto_tb tcg_gen_goto_tb_aarch64eb
#define tcg_gen_gvec_2 tcg_gen_gvec_2_aarch64eb
#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_aarch64eb
#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_aarch64eb
#define tcg_gen_gvec_3 tcg_gen_gvec_3_aarch64eb
#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_aarch64eb
#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_aarch64eb
#define tcg_gen_gvec_4 tcg_gen_gvec_4_aarch64eb
#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_aarch64eb
#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_aarch64eb
#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_aarch64eb
#define tcg_gen_gvec_add tcg_gen_gvec_add_aarch64eb
#define tcg_gen_gvec_and tcg_gen_gvec_and_aarch64eb
#define tcg_gen_gvec_andc tcg_gen_gvec_andc_aarch64eb
#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_aarch64eb
#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_aarch64eb
#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_aarch64eb
#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_aarch64eb
#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_aarch64eb
#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_aarch64eb
#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_aarch64eb
#define tcg_gen_gvec_mov tcg_gen_gvec_mov_aarch64eb
#define tcg_gen_gvec_neg tcg_gen_gvec_neg_aarch64eb
#define tcg_gen_gvec_not tcg_gen_gvec_not_aarch64eb
#define tcg_gen_gvec_or tcg_gen_gvec_or_aarch64eb
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_aarch64eb
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_aarch64eb
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_aarch64eb
#define tcg_gen_insn_start tcg_gen_insn_start_aarch64eb
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_aarch64eb
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_aarch64eb
@ -3205,6 +3259,15 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_aarch64eb
#define tcg_gen_subi_i32 tcg_gen_subi_i32_aarch64eb
#define tcg_gen_subi_i64 tcg_gen_subi_i64_aarch64eb
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_aarch64eb
#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_aarch64eb
#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_aarch64eb
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_aarch64eb
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_aarch64eb
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_aarch64eb
#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_aarch64eb
#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_aarch64eb
#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_aarch64eb
#define tcg_gen_xor_i32 tcg_gen_xor_i32_aarch64eb
#define tcg_gen_xor_i64 tcg_gen_xor_i64_aarch64eb
#define tcg_gen_xor_vec tcg_gen_xor_vec_aarch64eb

63
qemu/arm.h
View file

@ -401,6 +401,7 @@
#define dummy_c15_cp_reginfo dummy_c15_cp_reginfo_arm
#define dummy_func dummy_func_arm
#define dummy_section dummy_section_arm
#define dup_const_impl dup_const_impl_arm
#define end_list end_list_arm
#define ensure_writable_pages ensure_writable_pages_arm
#define eq128 eq128_arm
@ -1608,6 +1609,29 @@
#define helper_get_cp_reg64 helper_get_cp_reg64_arm
#define helper_get_r13_banked helper_get_r13_banked_arm
#define helper_get_user_reg helper_get_user_reg_arm
#define helper_gvec_add8 helper_gvec_add8_arm
#define helper_gvec_add16 helper_gvec_add16_arm
#define helper_gvec_add32 helper_gvec_add32_arm
#define helper_gvec_add64 helper_gvec_add64_arm
#define helper_gvec_and helper_gvec_and_arm
#define helper_gvec_andc helper_gvec_andc_arm
#define helper_gvec_dup8 helper_gvec_dup8_arm
#define helper_gvec_dup16 helper_gvec_dup16_arm
#define helper_gvec_dup32 helper_gvec_dup32_arm
#define helper_gvec_dup64 helper_gvec_dup64_arm
#define helper_gvec_mov helper_gvec_mov_arm
#define helper_gvec_neg8 helper_gvec_neg8_arm
#define helper_gvec_neg16 helper_gvec_neg16_arm
#define helper_gvec_neg32 helper_gvec_neg32_arm
#define helper_gvec_neg64 helper_gvec_neg64_arm
#define helper_gvec_not helper_gvec_not_arm
#define helper_gvec_or helper_gvec_or_arm
#define helper_gvec_orc helper_gvec_orc_arm
#define helper_gvec_sub8 helper_gvec_sub8_arm
#define helper_gvec_sub16 helper_gvec_sub16_arm
#define helper_gvec_sub32 helper_gvec_sub32_arm
#define helper_gvec_sub64 helper_gvec_sub64_arm
#define helper_gvec_xor helper_gvec_xor_arm
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_arm
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_arm
#define helper_iwmmxt_addcw helper_iwmmxt_addcw_arm
@ -2830,6 +2854,7 @@
#define shifter_out_im shifter_out_im_arm
#define shortShift128Left shortShift128Left_arm
#define shortShift192Left shortShift192Left_arm
#define simd_desc simd_desc_arm
#define simple_mpu_ap_bits simple_mpu_ap_bits_arm
#define size_code_gen_buffer size_code_gen_buffer_arm
#define softmmu_lock_user softmmu_lock_user_arm
@ -2985,6 +3010,7 @@
#define tcg_enabled tcg_enabled_arm
#define tcg_exec_all tcg_exec_all_arm
#define tcg_exec_init tcg_exec_init_arm
#define tcg_expand_vec_op tcg_expand_vec_op_arm
#define tcg_find_helper tcg_find_helper_arm
#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_arm
#define tcg_func_start tcg_func_start_arm
@ -3062,6 +3088,7 @@
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_arm
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_arm
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_arm
#define tcg_gen_dupi_vec tcg_gen_dupi_vec_arm
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_arm
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_arm
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_arm
@ -3086,6 +3113,33 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_arm
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_arm
#define tcg_gen_goto_tb tcg_gen_goto_tb_arm
#define tcg_gen_gvec_2 tcg_gen_gvec_2_arm
#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_arm
#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_arm
#define tcg_gen_gvec_3 tcg_gen_gvec_3_arm
#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_arm
#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_arm
#define tcg_gen_gvec_4 tcg_gen_gvec_4_arm
#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_arm
#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_arm
#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_arm
#define tcg_gen_gvec_add tcg_gen_gvec_add_arm
#define tcg_gen_gvec_and tcg_gen_gvec_and_arm
#define tcg_gen_gvec_andc tcg_gen_gvec_andc_arm
#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_arm
#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_arm
#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_arm
#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_arm
#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_arm
#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_arm
#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_arm
#define tcg_gen_gvec_mov tcg_gen_gvec_mov_arm
#define tcg_gen_gvec_neg tcg_gen_gvec_neg_arm
#define tcg_gen_gvec_not tcg_gen_gvec_not_arm
#define tcg_gen_gvec_or tcg_gen_gvec_or_arm
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_arm
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_arm
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_arm
#define tcg_gen_insn_start tcg_gen_insn_start_arm
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_arm
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_arm
@ -3205,6 +3259,15 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_arm
#define tcg_gen_subi_i32 tcg_gen_subi_i32_arm
#define tcg_gen_subi_i64 tcg_gen_subi_i64_arm
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_arm
#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_arm
#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_arm
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_arm
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_arm
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_arm
#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_arm
#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_arm
#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_arm
#define tcg_gen_xor_i32 tcg_gen_xor_i32_arm
#define tcg_gen_xor_i64 tcg_gen_xor_i64_arm
#define tcg_gen_xor_vec tcg_gen_xor_vec_arm

63
qemu/armeb.h
View file

@ -401,6 +401,7 @@
#define dummy_c15_cp_reginfo dummy_c15_cp_reginfo_armeb
#define dummy_func dummy_func_armeb
#define dummy_section dummy_section_armeb
#define dup_const_impl dup_const_impl_armeb
#define end_list end_list_armeb
#define ensure_writable_pages ensure_writable_pages_armeb
#define eq128 eq128_armeb
@ -1608,6 +1609,29 @@
#define helper_get_cp_reg64 helper_get_cp_reg64_armeb
#define helper_get_r13_banked helper_get_r13_banked_armeb
#define helper_get_user_reg helper_get_user_reg_armeb
#define helper_gvec_add8 helper_gvec_add8_armeb
#define helper_gvec_add16 helper_gvec_add16_armeb
#define helper_gvec_add32 helper_gvec_add32_armeb
#define helper_gvec_add64 helper_gvec_add64_armeb
#define helper_gvec_and helper_gvec_and_armeb
#define helper_gvec_andc helper_gvec_andc_armeb
#define helper_gvec_dup8 helper_gvec_dup8_armeb
#define helper_gvec_dup16 helper_gvec_dup16_armeb
#define helper_gvec_dup32 helper_gvec_dup32_armeb
#define helper_gvec_dup64 helper_gvec_dup64_armeb
#define helper_gvec_mov helper_gvec_mov_armeb
#define helper_gvec_neg8 helper_gvec_neg8_armeb
#define helper_gvec_neg16 helper_gvec_neg16_armeb
#define helper_gvec_neg32 helper_gvec_neg32_armeb
#define helper_gvec_neg64 helper_gvec_neg64_armeb
#define helper_gvec_not helper_gvec_not_armeb
#define helper_gvec_or helper_gvec_or_armeb
#define helper_gvec_orc helper_gvec_orc_armeb
#define helper_gvec_sub8 helper_gvec_sub8_armeb
#define helper_gvec_sub16 helper_gvec_sub16_armeb
#define helper_gvec_sub32 helper_gvec_sub32_armeb
#define helper_gvec_sub64 helper_gvec_sub64_armeb
#define helper_gvec_xor helper_gvec_xor_armeb
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_armeb
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_armeb
#define helper_iwmmxt_addcw helper_iwmmxt_addcw_armeb
@ -2830,6 +2854,7 @@
#define shifter_out_im shifter_out_im_armeb
#define shortShift128Left shortShift128Left_armeb
#define shortShift192Left shortShift192Left_armeb
#define simd_desc simd_desc_armeb
#define simple_mpu_ap_bits simple_mpu_ap_bits_armeb
#define size_code_gen_buffer size_code_gen_buffer_armeb
#define softmmu_lock_user softmmu_lock_user_armeb
@ -2985,6 +3010,7 @@
#define tcg_enabled tcg_enabled_armeb
#define tcg_exec_all tcg_exec_all_armeb
#define tcg_exec_init tcg_exec_init_armeb
#define tcg_expand_vec_op tcg_expand_vec_op_armeb
#define tcg_find_helper tcg_find_helper_armeb
#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_armeb
#define tcg_func_start tcg_func_start_armeb
@ -3062,6 +3088,7 @@
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_armeb
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_armeb
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_armeb
#define tcg_gen_dupi_vec tcg_gen_dupi_vec_armeb
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_armeb
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_armeb
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_armeb
@ -3086,6 +3113,33 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_armeb
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_armeb
#define tcg_gen_goto_tb tcg_gen_goto_tb_armeb
#define tcg_gen_gvec_2 tcg_gen_gvec_2_armeb
#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_armeb
#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_armeb
#define tcg_gen_gvec_3 tcg_gen_gvec_3_armeb
#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_armeb
#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_armeb
#define tcg_gen_gvec_4 tcg_gen_gvec_4_armeb
#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_armeb
#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_armeb
#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_armeb
#define tcg_gen_gvec_add tcg_gen_gvec_add_armeb
#define tcg_gen_gvec_and tcg_gen_gvec_and_armeb
#define tcg_gen_gvec_andc tcg_gen_gvec_andc_armeb
#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_armeb
#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_armeb
#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_armeb
#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_armeb
#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_armeb
#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_armeb
#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_armeb
#define tcg_gen_gvec_mov tcg_gen_gvec_mov_armeb
#define tcg_gen_gvec_neg tcg_gen_gvec_neg_armeb
#define tcg_gen_gvec_not tcg_gen_gvec_not_armeb
#define tcg_gen_gvec_or tcg_gen_gvec_or_armeb
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_armeb
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_armeb
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_armeb
#define tcg_gen_insn_start tcg_gen_insn_start_armeb
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_armeb
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_armeb
@ -3205,6 +3259,15 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_armeb
#define tcg_gen_subi_i32 tcg_gen_subi_i32_armeb
#define tcg_gen_subi_i64 tcg_gen_subi_i64_armeb
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_armeb
#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_armeb
#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_armeb
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_armeb
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_armeb
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_armeb
#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_armeb
#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_armeb
#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_armeb
#define tcg_gen_xor_i32 tcg_gen_xor_i32_armeb
#define tcg_gen_xor_i64 tcg_gen_xor_i64_armeb
#define tcg_gen_xor_vec tcg_gen_xor_vec_armeb

48
qemu/configure vendored
View file

@ -1086,6 +1086,50 @@ if compile_prog "" "" ; then
int128=yes
fi
########################################
# See if 16-byte vector operations are supported.
# Even without a vector unit the compiler may expand these.
# There is a bug in old GCC for PPC that crashes here.
# Unfortunately it's the system compiler for Centos 7.
cat > $TMPC << EOF
typedef unsigned char U1 __attribute__((vector_size(16)));
typedef unsigned short U2 __attribute__((vector_size(16)));
typedef unsigned int U4 __attribute__((vector_size(16)));
typedef unsigned long long U8 __attribute__((vector_size(16)));
typedef signed char S1 __attribute__((vector_size(16)));
typedef signed short S2 __attribute__((vector_size(16)));
typedef signed int S4 __attribute__((vector_size(16)));
typedef signed long long S8 __attribute__((vector_size(16)));
static U1 a1, b1;
static U2 a2, b2;
static U4 a4, b4;
static U8 a8, b8;
static S1 c1;
static S2 c2;
static S4 c4;
static S8 c8;
static int i;
int main(void)
{
a1 += b1; a2 += b2; a4 += b4; a8 += b8;
a1 -= b1; a2 -= b2; a4 -= b4; a8 -= b8;
a1 *= b1; a2 *= b2; a4 *= b4; a8 *= b8;
a1 &= b1; a2 &= b2; a4 &= b4; a8 &= b8;
a1 |= b1; a2 |= b2; a4 |= b4; a8 |= b8;
a1 ^= b1; a2 ^= b2; a4 ^= b4; a8 ^= b8;
a1 <<= i; a2 <<= i; a4 <<= i; a8 <<= i;
a1 >>= i; a2 >>= i; a4 >>= i; a8 >>= i;
c1 >>= i; c2 >>= i; c4 >>= i; c8 >>= i;
return 0;
}
EOF
vector16=no
if compile_prog "" "" ; then
vector16=yes
fi
#########################################
# See if 128-bit atomic operations are supported.
@ -1299,6 +1343,10 @@ if test "$atomic64" = "yes" ; then
echo "CONFIG_ATOMIC64=y" >> $config_host_mak
fi
if test "$vector16" = "yes" ; then
echo "CONFIG_VECTOR16=y" >> $config_host_mak
fi
if test "$tcg_interpreter" = "yes"; then
QEMU_INCLUDES="-I\$(SRC_PATH)/tcg/tci $QEMU_INCLUDES"
elif test "$ARCH" = "sparc64" ; then

63
qemu/header_gen.py
View file

@ -407,6 +407,7 @@ symbols = (
'dummy_c15_cp_reginfo',
'dummy_func',
'dummy_section',
'dup_const_impl',
'end_list',
'ensure_writable_pages',
'eq128',
@ -1614,6 +1615,29 @@ symbols = (
'helper_get_cp_reg64',
'helper_get_r13_banked',
'helper_get_user_reg',
'helper_gvec_add8',
'helper_gvec_add16',
'helper_gvec_add32',
'helper_gvec_add64',
'helper_gvec_and',
'helper_gvec_andc',
'helper_gvec_dup8',
'helper_gvec_dup16',
'helper_gvec_dup32',
'helper_gvec_dup64',
'helper_gvec_mov',
'helper_gvec_neg8',
'helper_gvec_neg16',
'helper_gvec_neg32',
'helper_gvec_neg64',
'helper_gvec_not',
'helper_gvec_or',
'helper_gvec_orc',
'helper_gvec_sub8',
'helper_gvec_sub16',
'helper_gvec_sub32',
'helper_gvec_sub64',
'helper_gvec_xor',
'helper_iwmmxt_addcb',
'helper_iwmmxt_addcl',
'helper_iwmmxt_addcw',
@ -2836,6 +2860,7 @@ symbols = (
'shifter_out_im',
'shortShift128Left',
'shortShift192Left',
'simd_desc',
'simple_mpu_ap_bits',
'size_code_gen_buffer',
'softmmu_lock_user',
@ -2991,6 +3016,7 @@ symbols = (
'tcg_enabled',
'tcg_exec_all',
'tcg_exec_init',
'tcg_expand_vec_op',
'tcg_find_helper',
'tcg_flush_softmmu_tlb',
'tcg_func_start',
@ -3068,6 +3094,7 @@ symbols = (
'tcg_gen_dup16i_vec',
'tcg_gen_dup32i_vec',
'tcg_gen_dup64i_vec',
'tcg_gen_dupi_vec',
'tcg_gen_dup_i32_vec',
'tcg_gen_dup_i64_vec',
'tcg_gen_eqv_i32',
@ -3092,6 +3119,33 @@ symbols = (
'tcg_gen_extrl_i64_i32',
'tcg_gen_extu_i32_i64',
'tcg_gen_goto_tb',
'tcg_gen_gvec_2',
'tcg_gen_gvec_2_ool',
'tcg_gen_gvec_2_ptr',
'tcg_gen_gvec_3',
'tcg_gen_gvec_3_ool',
'tcg_gen_gvec_3_ptr',
'tcg_gen_gvec_4',
'tcg_gen_gvec_4_ool',
'tcg_gen_gvec_4_ptr',
'tcg_gen_gvec_5_ool',
'tcg_gen_gvec_add',
'tcg_gen_gvec_and',
'tcg_gen_gvec_andc',
'tcg_gen_gvec_dup8i',
'tcg_gen_gvec_dup16i',
'tcg_gen_gvec_dup32i',
'tcg_gen_gvec_dup64i',
'tcg_gen_gvec_dup_i32',
'tcg_gen_gvec_dup_i64',
'tcg_gen_gvec_dup_mem',
'tcg_gen_gvec_mov',
'tcg_gen_gvec_neg',
'tcg_gen_gvec_not',
'tcg_gen_gvec_or',
'tcg_gen_gvec_orc',
'tcg_gen_gvec_sub',
'tcg_gen_gvec_xor',
'tcg_gen_insn_start',
'tcg_gen_ld16s_i64',
'tcg_gen_ld16u_i64',
@ -3211,6 +3265,15 @@ symbols = (
'tcg_gen_subfi_i64',
'tcg_gen_subi_i32',
'tcg_gen_subi_i64',
'tcg_gen_vec_add8_i64',
'tcg_gen_vec_add16_i64',
'tcg_gen_vec_add32_i64',
'tcg_gen_vec_neg8_i64',
'tcg_gen_vec_neg16_i64',
'tcg_gen_vec_neg32_i64',
'tcg_gen_vec_sub8_i64',
'tcg_gen_vec_sub16_i64',
'tcg_gen_vec_sub32_i64',
'tcg_gen_xor_i32',
'tcg_gen_xor_i64',
'tcg_gen_xor_vec',

63
qemu/m68k.h
View file

@ -401,6 +401,7 @@
#define dummy_c15_cp_reginfo dummy_c15_cp_reginfo_m68k
#define dummy_func dummy_func_m68k
#define dummy_section dummy_section_m68k
#define dup_const_impl dup_const_impl_m68k
#define end_list end_list_m68k
#define ensure_writable_pages ensure_writable_pages_m68k
#define eq128 eq128_m68k
@ -1608,6 +1609,29 @@
#define helper_get_cp_reg64 helper_get_cp_reg64_m68k
#define helper_get_r13_banked helper_get_r13_banked_m68k
#define helper_get_user_reg helper_get_user_reg_m68k
#define helper_gvec_add8 helper_gvec_add8_m68k
#define helper_gvec_add16 helper_gvec_add16_m68k
#define helper_gvec_add32 helper_gvec_add32_m68k
#define helper_gvec_add64 helper_gvec_add64_m68k
#define helper_gvec_and helper_gvec_and_m68k
#define helper_gvec_andc helper_gvec_andc_m68k
#define helper_gvec_dup8 helper_gvec_dup8_m68k
#define helper_gvec_dup16 helper_gvec_dup16_m68k
#define helper_gvec_dup32 helper_gvec_dup32_m68k
#define helper_gvec_dup64 helper_gvec_dup64_m68k
#define helper_gvec_mov helper_gvec_mov_m68k
#define helper_gvec_neg8 helper_gvec_neg8_m68k
#define helper_gvec_neg16 helper_gvec_neg16_m68k
#define helper_gvec_neg32 helper_gvec_neg32_m68k
#define helper_gvec_neg64 helper_gvec_neg64_m68k
#define helper_gvec_not helper_gvec_not_m68k
#define helper_gvec_or helper_gvec_or_m68k
#define helper_gvec_orc helper_gvec_orc_m68k
#define helper_gvec_sub8 helper_gvec_sub8_m68k
#define helper_gvec_sub16 helper_gvec_sub16_m68k
#define helper_gvec_sub32 helper_gvec_sub32_m68k
#define helper_gvec_sub64 helper_gvec_sub64_m68k
#define helper_gvec_xor helper_gvec_xor_m68k
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_m68k
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_m68k
#define helper_iwmmxt_addcw helper_iwmmxt_addcw_m68k
@ -2830,6 +2854,7 @@
#define shifter_out_im shifter_out_im_m68k
#define shortShift128Left shortShift128Left_m68k
#define shortShift192Left shortShift192Left_m68k
#define simd_desc simd_desc_m68k
#define simple_mpu_ap_bits simple_mpu_ap_bits_m68k
#define size_code_gen_buffer size_code_gen_buffer_m68k
#define softmmu_lock_user softmmu_lock_user_m68k
@ -2985,6 +3010,7 @@
#define tcg_enabled tcg_enabled_m68k
#define tcg_exec_all tcg_exec_all_m68k
#define tcg_exec_init tcg_exec_init_m68k
#define tcg_expand_vec_op tcg_expand_vec_op_m68k
#define tcg_find_helper tcg_find_helper_m68k
#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_m68k
#define tcg_func_start tcg_func_start_m68k
@ -3062,6 +3088,7 @@
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_m68k
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_m68k
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_m68k
#define tcg_gen_dupi_vec tcg_gen_dupi_vec_m68k
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_m68k
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_m68k
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_m68k
@ -3086,6 +3113,33 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_m68k
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_m68k
#define tcg_gen_goto_tb tcg_gen_goto_tb_m68k
#define tcg_gen_gvec_2 tcg_gen_gvec_2_m68k
#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_m68k
#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_m68k
#define tcg_gen_gvec_3 tcg_gen_gvec_3_m68k
#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_m68k
#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_m68k
#define tcg_gen_gvec_4 tcg_gen_gvec_4_m68k
#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_m68k
#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_m68k
#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_m68k
#define tcg_gen_gvec_add tcg_gen_gvec_add_m68k
#define tcg_gen_gvec_and tcg_gen_gvec_and_m68k
#define tcg_gen_gvec_andc tcg_gen_gvec_andc_m68k
#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_m68k
#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_m68k
#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_m68k
#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_m68k
#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_m68k
#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_m68k
#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_m68k
#define tcg_gen_gvec_mov tcg_gen_gvec_mov_m68k
#define tcg_gen_gvec_neg tcg_gen_gvec_neg_m68k
#define tcg_gen_gvec_not tcg_gen_gvec_not_m68k
#define tcg_gen_gvec_or tcg_gen_gvec_or_m68k
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_m68k
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_m68k
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_m68k
#define tcg_gen_insn_start tcg_gen_insn_start_m68k
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_m68k
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_m68k
@ -3205,6 +3259,15 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_m68k
#define tcg_gen_subi_i32 tcg_gen_subi_i32_m68k
#define tcg_gen_subi_i64 tcg_gen_subi_i64_m68k
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_m68k
#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_m68k
#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_m68k
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_m68k
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_m68k
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_m68k
#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_m68k
#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_m68k
#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_m68k
#define tcg_gen_xor_i32 tcg_gen_xor_i32_m68k
#define tcg_gen_xor_i64 tcg_gen_xor_i64_m68k
#define tcg_gen_xor_vec tcg_gen_xor_vec_m68k

63
qemu/mips.h
View file

@ -401,6 +401,7 @@
#define dummy_c15_cp_reginfo dummy_c15_cp_reginfo_mips
#define dummy_func dummy_func_mips
#define dummy_section dummy_section_mips
#define dup_const_impl dup_const_impl_mips
#define end_list end_list_mips
#define ensure_writable_pages ensure_writable_pages_mips
#define eq128 eq128_mips
@ -1608,6 +1609,29 @@
#define helper_get_cp_reg64 helper_get_cp_reg64_mips
#define helper_get_r13_banked helper_get_r13_banked_mips
#define helper_get_user_reg helper_get_user_reg_mips
#define helper_gvec_add8 helper_gvec_add8_mips
#define helper_gvec_add16 helper_gvec_add16_mips
#define helper_gvec_add32 helper_gvec_add32_mips
#define helper_gvec_add64 helper_gvec_add64_mips
#define helper_gvec_and helper_gvec_and_mips
#define helper_gvec_andc helper_gvec_andc_mips
#define helper_gvec_dup8 helper_gvec_dup8_mips
#define helper_gvec_dup16 helper_gvec_dup16_mips
#define helper_gvec_dup32 helper_gvec_dup32_mips
#define helper_gvec_dup64 helper_gvec_dup64_mips
#define helper_gvec_mov helper_gvec_mov_mips
#define helper_gvec_neg8 helper_gvec_neg8_mips
#define helper_gvec_neg16 helper_gvec_neg16_mips
#define helper_gvec_neg32 helper_gvec_neg32_mips
#define helper_gvec_neg64 helper_gvec_neg64_mips
#define helper_gvec_not helper_gvec_not_mips
#define helper_gvec_or helper_gvec_or_mips
#define helper_gvec_orc helper_gvec_orc_mips
#define helper_gvec_sub8 helper_gvec_sub8_mips
#define helper_gvec_sub16 helper_gvec_sub16_mips
#define helper_gvec_sub32 helper_gvec_sub32_mips
#define helper_gvec_sub64 helper_gvec_sub64_mips
#define helper_gvec_xor helper_gvec_xor_mips
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_mips
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_mips
#define helper_iwmmxt_addcw helper_iwmmxt_addcw_mips
@ -2830,6 +2854,7 @@
#define shifter_out_im shifter_out_im_mips
#define shortShift128Left shortShift128Left_mips
#define shortShift192Left shortShift192Left_mips
#define simd_desc simd_desc_mips
#define simple_mpu_ap_bits simple_mpu_ap_bits_mips
#define size_code_gen_buffer size_code_gen_buffer_mips
#define softmmu_lock_user softmmu_lock_user_mips
@ -2985,6 +3010,7 @@
#define tcg_enabled tcg_enabled_mips
#define tcg_exec_all tcg_exec_all_mips
#define tcg_exec_init tcg_exec_init_mips
#define tcg_expand_vec_op tcg_expand_vec_op_mips
#define tcg_find_helper tcg_find_helper_mips
#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_mips
#define tcg_func_start tcg_func_start_mips
@ -3062,6 +3088,7 @@
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_mips
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_mips
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_mips
#define tcg_gen_dupi_vec tcg_gen_dupi_vec_mips
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_mips
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_mips
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_mips
@ -3086,6 +3113,33 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_mips
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mips
#define tcg_gen_goto_tb tcg_gen_goto_tb_mips
#define tcg_gen_gvec_2 tcg_gen_gvec_2_mips
#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_mips
#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_mips
#define tcg_gen_gvec_3 tcg_gen_gvec_3_mips
#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_mips
#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_mips
#define tcg_gen_gvec_4 tcg_gen_gvec_4_mips
#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_mips
#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_mips
#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_mips
#define tcg_gen_gvec_add tcg_gen_gvec_add_mips
#define tcg_gen_gvec_and tcg_gen_gvec_and_mips
#define tcg_gen_gvec_andc tcg_gen_gvec_andc_mips
#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_mips
#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_mips
#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_mips
#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_mips
#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_mips
#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_mips
#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_mips
#define tcg_gen_gvec_mov tcg_gen_gvec_mov_mips
#define tcg_gen_gvec_neg tcg_gen_gvec_neg_mips
#define tcg_gen_gvec_not tcg_gen_gvec_not_mips
#define tcg_gen_gvec_or tcg_gen_gvec_or_mips
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_mips
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_mips
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_mips
#define tcg_gen_insn_start tcg_gen_insn_start_mips
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_mips
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_mips
@ -3205,6 +3259,15 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mips
#define tcg_gen_subi_i32 tcg_gen_subi_i32_mips
#define tcg_gen_subi_i64 tcg_gen_subi_i64_mips
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_mips
#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_mips
#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_mips
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_mips
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_mips
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_mips
#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_mips
#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_mips
#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_mips
#define tcg_gen_xor_i32 tcg_gen_xor_i32_mips
#define tcg_gen_xor_i64 tcg_gen_xor_i64_mips
#define tcg_gen_xor_vec tcg_gen_xor_vec_mips

63
qemu/mips64.h
View file

@ -401,6 +401,7 @@
#define dummy_c15_cp_reginfo dummy_c15_cp_reginfo_mips64
#define dummy_func dummy_func_mips64
#define dummy_section dummy_section_mips64
#define dup_const_impl dup_const_impl_mips64
#define end_list end_list_mips64
#define ensure_writable_pages ensure_writable_pages_mips64
#define eq128 eq128_mips64
@ -1608,6 +1609,29 @@
#define helper_get_cp_reg64 helper_get_cp_reg64_mips64
#define helper_get_r13_banked helper_get_r13_banked_mips64
#define helper_get_user_reg helper_get_user_reg_mips64
#define helper_gvec_add8 helper_gvec_add8_mips64
#define helper_gvec_add16 helper_gvec_add16_mips64
#define helper_gvec_add32 helper_gvec_add32_mips64
#define helper_gvec_add64 helper_gvec_add64_mips64
#define helper_gvec_and helper_gvec_and_mips64
#define helper_gvec_andc helper_gvec_andc_mips64
#define helper_gvec_dup8 helper_gvec_dup8_mips64
#define helper_gvec_dup16 helper_gvec_dup16_mips64
#define helper_gvec_dup32 helper_gvec_dup32_mips64
#define helper_gvec_dup64 helper_gvec_dup64_mips64
#define helper_gvec_mov helper_gvec_mov_mips64
#define helper_gvec_neg8 helper_gvec_neg8_mips64
#define helper_gvec_neg16 helper_gvec_neg16_mips64
#define helper_gvec_neg32 helper_gvec_neg32_mips64
#define helper_gvec_neg64 helper_gvec_neg64_mips64
#define helper_gvec_not helper_gvec_not_mips64
#define helper_gvec_or helper_gvec_or_mips64
#define helper_gvec_orc helper_gvec_orc_mips64
#define helper_gvec_sub8 helper_gvec_sub8_mips64
#define helper_gvec_sub16 helper_gvec_sub16_mips64
#define helper_gvec_sub32 helper_gvec_sub32_mips64
#define helper_gvec_sub64 helper_gvec_sub64_mips64
#define helper_gvec_xor helper_gvec_xor_mips64
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_mips64
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_mips64
#define helper_iwmmxt_addcw helper_iwmmxt_addcw_mips64
@ -2830,6 +2854,7 @@
#define shifter_out_im shifter_out_im_mips64
#define shortShift128Left shortShift128Left_mips64
#define shortShift192Left shortShift192Left_mips64
#define simd_desc simd_desc_mips64
#define simple_mpu_ap_bits simple_mpu_ap_bits_mips64
#define size_code_gen_buffer size_code_gen_buffer_mips64
#define softmmu_lock_user softmmu_lock_user_mips64
@ -2985,6 +3010,7 @@
#define tcg_enabled tcg_enabled_mips64
#define tcg_exec_all tcg_exec_all_mips64
#define tcg_exec_init tcg_exec_init_mips64
#define tcg_expand_vec_op tcg_expand_vec_op_mips64
#define tcg_find_helper tcg_find_helper_mips64
#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_mips64
#define tcg_func_start tcg_func_start_mips64
@ -3062,6 +3088,7 @@
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_mips64
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_mips64
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_mips64
#define tcg_gen_dupi_vec tcg_gen_dupi_vec_mips64
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_mips64
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_mips64
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_mips64
@ -3086,6 +3113,33 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_mips64
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mips64
#define tcg_gen_goto_tb tcg_gen_goto_tb_mips64
#define tcg_gen_gvec_2 tcg_gen_gvec_2_mips64
#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_mips64
#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_mips64
#define tcg_gen_gvec_3 tcg_gen_gvec_3_mips64
#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_mips64
#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_mips64
#define tcg_gen_gvec_4 tcg_gen_gvec_4_mips64
#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_mips64
#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_mips64
#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_mips64
#define tcg_gen_gvec_add tcg_gen_gvec_add_mips64
#define tcg_gen_gvec_and tcg_gen_gvec_and_mips64
#define tcg_gen_gvec_andc tcg_gen_gvec_andc_mips64
#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_mips64
#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_mips64
#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_mips64
#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_mips64
#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_mips64
#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_mips64
#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_mips64
#define tcg_gen_gvec_mov tcg_gen_gvec_mov_mips64
#define tcg_gen_gvec_neg tcg_gen_gvec_neg_mips64
#define tcg_gen_gvec_not tcg_gen_gvec_not_mips64
#define tcg_gen_gvec_or tcg_gen_gvec_or_mips64
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_mips64
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_mips64
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_mips64
#define tcg_gen_insn_start tcg_gen_insn_start_mips64
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_mips64
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_mips64
@ -3205,6 +3259,15 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mips64
#define tcg_gen_subi_i32 tcg_gen_subi_i32_mips64
#define tcg_gen_subi_i64 tcg_gen_subi_i64_mips64
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_mips64
#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_mips64
#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_mips64
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_mips64
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_mips64
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_mips64
#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_mips64
#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_mips64
#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_mips64
#define tcg_gen_xor_i32 tcg_gen_xor_i32_mips64
#define tcg_gen_xor_i64 tcg_gen_xor_i64_mips64
#define tcg_gen_xor_vec tcg_gen_xor_vec_mips64

63
qemu/mips64el.h
View file

@ -401,6 +401,7 @@
#define dummy_c15_cp_reginfo dummy_c15_cp_reginfo_mips64el
#define dummy_func dummy_func_mips64el
#define dummy_section dummy_section_mips64el
#define dup_const_impl dup_const_impl_mips64el
#define end_list end_list_mips64el
#define ensure_writable_pages ensure_writable_pages_mips64el
#define eq128 eq128_mips64el
@ -1608,6 +1609,29 @@
#define helper_get_cp_reg64 helper_get_cp_reg64_mips64el
#define helper_get_r13_banked helper_get_r13_banked_mips64el
#define helper_get_user_reg helper_get_user_reg_mips64el
#define helper_gvec_add8 helper_gvec_add8_mips64el
#define helper_gvec_add16 helper_gvec_add16_mips64el
#define helper_gvec_add32 helper_gvec_add32_mips64el
#define helper_gvec_add64 helper_gvec_add64_mips64el
#define helper_gvec_and helper_gvec_and_mips64el
#define helper_gvec_andc helper_gvec_andc_mips64el
#define helper_gvec_dup8 helper_gvec_dup8_mips64el
#define helper_gvec_dup16 helper_gvec_dup16_mips64el
#define helper_gvec_dup32 helper_gvec_dup32_mips64el
#define helper_gvec_dup64 helper_gvec_dup64_mips64el
#define helper_gvec_mov helper_gvec_mov_mips64el
#define helper_gvec_neg8 helper_gvec_neg8_mips64el
#define helper_gvec_neg16 helper_gvec_neg16_mips64el
#define helper_gvec_neg32 helper_gvec_neg32_mips64el
#define helper_gvec_neg64 helper_gvec_neg64_mips64el
#define helper_gvec_not helper_gvec_not_mips64el
#define helper_gvec_or helper_gvec_or_mips64el
#define helper_gvec_orc helper_gvec_orc_mips64el
#define helper_gvec_sub8 helper_gvec_sub8_mips64el
#define helper_gvec_sub16 helper_gvec_sub16_mips64el
#define helper_gvec_sub32 helper_gvec_sub32_mips64el
#define helper_gvec_sub64 helper_gvec_sub64_mips64el
#define helper_gvec_xor helper_gvec_xor_mips64el
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_mips64el
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_mips64el
#define helper_iwmmxt_addcw helper_iwmmxt_addcw_mips64el
@ -2830,6 +2854,7 @@
#define shifter_out_im shifter_out_im_mips64el
#define shortShift128Left shortShift128Left_mips64el
#define shortShift192Left shortShift192Left_mips64el
#define simd_desc simd_desc_mips64el
#define simple_mpu_ap_bits simple_mpu_ap_bits_mips64el
#define size_code_gen_buffer size_code_gen_buffer_mips64el
#define softmmu_lock_user softmmu_lock_user_mips64el
@ -2985,6 +3010,7 @@
#define tcg_enabled tcg_enabled_mips64el
#define tcg_exec_all tcg_exec_all_mips64el
#define tcg_exec_init tcg_exec_init_mips64el
#define tcg_expand_vec_op tcg_expand_vec_op_mips64el
#define tcg_find_helper tcg_find_helper_mips64el
#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_mips64el
#define tcg_func_start tcg_func_start_mips64el
@ -3062,6 +3088,7 @@
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_mips64el
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_mips64el
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_mips64el
#define tcg_gen_dupi_vec tcg_gen_dupi_vec_mips64el
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_mips64el
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_mips64el
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_mips64el
@ -3086,6 +3113,33 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_mips64el
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mips64el
#define tcg_gen_goto_tb tcg_gen_goto_tb_mips64el
#define tcg_gen_gvec_2 tcg_gen_gvec_2_mips64el
#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_mips64el
#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_mips64el
#define tcg_gen_gvec_3 tcg_gen_gvec_3_mips64el
#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_mips64el
#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_mips64el
#define tcg_gen_gvec_4 tcg_gen_gvec_4_mips64el
#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_mips64el
#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_mips64el
#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_mips64el
#define tcg_gen_gvec_add tcg_gen_gvec_add_mips64el
#define tcg_gen_gvec_and tcg_gen_gvec_and_mips64el
#define tcg_gen_gvec_andc tcg_gen_gvec_andc_mips64el
#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_mips64el
#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_mips64el
#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_mips64el
#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_mips64el
#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_mips64el
#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_mips64el
#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_mips64el
#define tcg_gen_gvec_mov tcg_gen_gvec_mov_mips64el
#define tcg_gen_gvec_neg tcg_gen_gvec_neg_mips64el
#define tcg_gen_gvec_not tcg_gen_gvec_not_mips64el
#define tcg_gen_gvec_or tcg_gen_gvec_or_mips64el
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_mips64el
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_mips64el
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_mips64el
#define tcg_gen_insn_start tcg_gen_insn_start_mips64el
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_mips64el
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_mips64el
@ -3205,6 +3259,15 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mips64el
#define tcg_gen_subi_i32 tcg_gen_subi_i32_mips64el
#define tcg_gen_subi_i64 tcg_gen_subi_i64_mips64el
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_mips64el
#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_mips64el
#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_mips64el
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_mips64el
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_mips64el
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_mips64el
#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_mips64el
#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_mips64el
#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_mips64el
#define tcg_gen_xor_i32 tcg_gen_xor_i32_mips64el
#define tcg_gen_xor_i64 tcg_gen_xor_i64_mips64el
#define tcg_gen_xor_vec tcg_gen_xor_vec_mips64el

63
qemu/mipsel.h
View file

@ -401,6 +401,7 @@
#define dummy_c15_cp_reginfo dummy_c15_cp_reginfo_mipsel
#define dummy_func dummy_func_mipsel
#define dummy_section dummy_section_mipsel
#define dup_const_impl dup_const_impl_mipsel
#define end_list end_list_mipsel
#define ensure_writable_pages ensure_writable_pages_mipsel
#define eq128 eq128_mipsel
@ -1608,6 +1609,29 @@
#define helper_get_cp_reg64 helper_get_cp_reg64_mipsel
#define helper_get_r13_banked helper_get_r13_banked_mipsel
#define helper_get_user_reg helper_get_user_reg_mipsel
#define helper_gvec_add8 helper_gvec_add8_mipsel
#define helper_gvec_add16 helper_gvec_add16_mipsel
#define helper_gvec_add32 helper_gvec_add32_mipsel
#define helper_gvec_add64 helper_gvec_add64_mipsel
#define helper_gvec_and helper_gvec_and_mipsel
#define helper_gvec_andc helper_gvec_andc_mipsel
#define helper_gvec_dup8 helper_gvec_dup8_mipsel
#define helper_gvec_dup16 helper_gvec_dup16_mipsel
#define helper_gvec_dup32 helper_gvec_dup32_mipsel
#define helper_gvec_dup64 helper_gvec_dup64_mipsel
#define helper_gvec_mov helper_gvec_mov_mipsel
#define helper_gvec_neg8 helper_gvec_neg8_mipsel
#define helper_gvec_neg16 helper_gvec_neg16_mipsel
#define helper_gvec_neg32 helper_gvec_neg32_mipsel
#define helper_gvec_neg64 helper_gvec_neg64_mipsel
#define helper_gvec_not helper_gvec_not_mipsel
#define helper_gvec_or helper_gvec_or_mipsel
#define helper_gvec_orc helper_gvec_orc_mipsel
#define helper_gvec_sub8 helper_gvec_sub8_mipsel
#define helper_gvec_sub16 helper_gvec_sub16_mipsel
#define helper_gvec_sub32 helper_gvec_sub32_mipsel
#define helper_gvec_sub64 helper_gvec_sub64_mipsel
#define helper_gvec_xor helper_gvec_xor_mipsel
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_mipsel
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_mipsel
#define helper_iwmmxt_addcw helper_iwmmxt_addcw_mipsel
@ -2830,6 +2854,7 @@
#define shifter_out_im shifter_out_im_mipsel
#define shortShift128Left shortShift128Left_mipsel
#define shortShift192Left shortShift192Left_mipsel
#define simd_desc simd_desc_mipsel
#define simple_mpu_ap_bits simple_mpu_ap_bits_mipsel
#define size_code_gen_buffer size_code_gen_buffer_mipsel
#define softmmu_lock_user softmmu_lock_user_mipsel
@ -2985,6 +3010,7 @@
#define tcg_enabled tcg_enabled_mipsel
#define tcg_exec_all tcg_exec_all_mipsel
#define tcg_exec_init tcg_exec_init_mipsel
#define tcg_expand_vec_op tcg_expand_vec_op_mipsel
#define tcg_find_helper tcg_find_helper_mipsel
#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_mipsel
#define tcg_func_start tcg_func_start_mipsel
@ -3062,6 +3088,7 @@
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_mipsel
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_mipsel
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_mipsel
#define tcg_gen_dupi_vec tcg_gen_dupi_vec_mipsel
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_mipsel
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_mipsel
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_mipsel
@ -3086,6 +3113,33 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_mipsel
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mipsel
#define tcg_gen_goto_tb tcg_gen_goto_tb_mipsel
#define tcg_gen_gvec_2 tcg_gen_gvec_2_mipsel
#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_mipsel
#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_mipsel
#define tcg_gen_gvec_3 tcg_gen_gvec_3_mipsel
#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_mipsel
#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_mipsel
#define tcg_gen_gvec_4 tcg_gen_gvec_4_mipsel
#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_mipsel
#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_mipsel
#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_mipsel
#define tcg_gen_gvec_add tcg_gen_gvec_add_mipsel
#define tcg_gen_gvec_and tcg_gen_gvec_and_mipsel
#define tcg_gen_gvec_andc tcg_gen_gvec_andc_mipsel
#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_mipsel
#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_mipsel
#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_mipsel
#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_mipsel
#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_mipsel
#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_mipsel
#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_mipsel
#define tcg_gen_gvec_mov tcg_gen_gvec_mov_mipsel
#define tcg_gen_gvec_neg tcg_gen_gvec_neg_mipsel
#define tcg_gen_gvec_not tcg_gen_gvec_not_mipsel
#define tcg_gen_gvec_or tcg_gen_gvec_or_mipsel
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_mipsel
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_mipsel
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_mipsel
#define tcg_gen_insn_start tcg_gen_insn_start_mipsel
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_mipsel
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_mipsel
@ -3205,6 +3259,15 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mipsel
#define tcg_gen_subi_i32 tcg_gen_subi_i32_mipsel
#define tcg_gen_subi_i64 tcg_gen_subi_i64_mipsel
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_mipsel
#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_mipsel
#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_mipsel
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_mipsel
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_mipsel
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_mipsel
#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_mipsel
#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_mipsel
#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_mipsel
#define tcg_gen_xor_i32 tcg_gen_xor_i32_mipsel
#define tcg_gen_xor_i64 tcg_gen_xor_i64_mipsel
#define tcg_gen_xor_vec tcg_gen_xor_vec_mipsel

63
qemu/powerpc.h
View file

@ -401,6 +401,7 @@
#define dummy_c15_cp_reginfo dummy_c15_cp_reginfo_powerpc
#define dummy_func dummy_func_powerpc
#define dummy_section dummy_section_powerpc
#define dup_const_impl dup_const_impl_powerpc
#define end_list end_list_powerpc
#define ensure_writable_pages ensure_writable_pages_powerpc
#define eq128 eq128_powerpc
@ -1608,6 +1609,29 @@
#define helper_get_cp_reg64 helper_get_cp_reg64_powerpc
#define helper_get_r13_banked helper_get_r13_banked_powerpc
#define helper_get_user_reg helper_get_user_reg_powerpc
#define helper_gvec_add8 helper_gvec_add8_powerpc
#define helper_gvec_add16 helper_gvec_add16_powerpc
#define helper_gvec_add32 helper_gvec_add32_powerpc
#define helper_gvec_add64 helper_gvec_add64_powerpc
#define helper_gvec_and helper_gvec_and_powerpc
#define helper_gvec_andc helper_gvec_andc_powerpc
#define helper_gvec_dup8 helper_gvec_dup8_powerpc
#define helper_gvec_dup16 helper_gvec_dup16_powerpc
#define helper_gvec_dup32 helper_gvec_dup32_powerpc
#define helper_gvec_dup64 helper_gvec_dup64_powerpc
#define helper_gvec_mov helper_gvec_mov_powerpc
#define helper_gvec_neg8 helper_gvec_neg8_powerpc
#define helper_gvec_neg16 helper_gvec_neg16_powerpc
#define helper_gvec_neg32 helper_gvec_neg32_powerpc
#define helper_gvec_neg64 helper_gvec_neg64_powerpc
#define helper_gvec_not helper_gvec_not_powerpc
#define helper_gvec_or helper_gvec_or_powerpc
#define helper_gvec_orc helper_gvec_orc_powerpc
#define helper_gvec_sub8 helper_gvec_sub8_powerpc
#define helper_gvec_sub16 helper_gvec_sub16_powerpc
#define helper_gvec_sub32 helper_gvec_sub32_powerpc
#define helper_gvec_sub64 helper_gvec_sub64_powerpc
#define helper_gvec_xor helper_gvec_xor_powerpc
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_powerpc
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_powerpc
#define helper_iwmmxt_addcw helper_iwmmxt_addcw_powerpc
@ -2830,6 +2854,7 @@
#define shifter_out_im shifter_out_im_powerpc
#define shortShift128Left shortShift128Left_powerpc
#define shortShift192Left shortShift192Left_powerpc
#define simd_desc simd_desc_powerpc
#define simple_mpu_ap_bits simple_mpu_ap_bits_powerpc
#define size_code_gen_buffer size_code_gen_buffer_powerpc
#define softmmu_lock_user softmmu_lock_user_powerpc
@ -2985,6 +3010,7 @@
#define tcg_enabled tcg_enabled_powerpc
#define tcg_exec_all tcg_exec_all_powerpc
#define tcg_exec_init tcg_exec_init_powerpc
#define tcg_expand_vec_op tcg_expand_vec_op_powerpc
#define tcg_find_helper tcg_find_helper_powerpc
#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_powerpc
#define tcg_func_start tcg_func_start_powerpc
@ -3062,6 +3088,7 @@
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_powerpc
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_powerpc
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_powerpc
#define tcg_gen_dupi_vec tcg_gen_dupi_vec_powerpc
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_powerpc
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_powerpc
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_powerpc
@ -3086,6 +3113,33 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_powerpc
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_powerpc
#define tcg_gen_goto_tb tcg_gen_goto_tb_powerpc
#define tcg_gen_gvec_2 tcg_gen_gvec_2_powerpc
#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_powerpc
#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_powerpc
#define tcg_gen_gvec_3 tcg_gen_gvec_3_powerpc
#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_powerpc
#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_powerpc
#define tcg_gen_gvec_4 tcg_gen_gvec_4_powerpc
#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_powerpc
#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_powerpc
#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_powerpc
#define tcg_gen_gvec_add tcg_gen_gvec_add_powerpc
#define tcg_gen_gvec_and tcg_gen_gvec_and_powerpc
#define tcg_gen_gvec_andc tcg_gen_gvec_andc_powerpc
#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_powerpc
#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_powerpc
#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_powerpc
#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_powerpc
#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_powerpc
#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_powerpc
#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_powerpc
#define tcg_gen_gvec_mov tcg_gen_gvec_mov_powerpc
#define tcg_gen_gvec_neg tcg_gen_gvec_neg_powerpc
#define tcg_gen_gvec_not tcg_gen_gvec_not_powerpc
#define tcg_gen_gvec_or tcg_gen_gvec_or_powerpc
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_powerpc
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_powerpc
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_powerpc
#define tcg_gen_insn_start tcg_gen_insn_start_powerpc
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_powerpc
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_powerpc
@ -3205,6 +3259,15 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_powerpc
#define tcg_gen_subi_i32 tcg_gen_subi_i32_powerpc
#define tcg_gen_subi_i64 tcg_gen_subi_i64_powerpc
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_powerpc
#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_powerpc
#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_powerpc
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_powerpc
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_powerpc
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_powerpc
#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_powerpc
#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_powerpc
#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_powerpc
#define tcg_gen_xor_i32 tcg_gen_xor_i32_powerpc
#define tcg_gen_xor_i64 tcg_gen_xor_i64_powerpc
#define tcg_gen_xor_vec tcg_gen_xor_vec_powerpc

63
qemu/sparc.h
View file

@ -401,6 +401,7 @@
#define dummy_c15_cp_reginfo dummy_c15_cp_reginfo_sparc
#define dummy_func dummy_func_sparc
#define dummy_section dummy_section_sparc
#define dup_const_impl dup_const_impl_sparc
#define end_list end_list_sparc
#define ensure_writable_pages ensure_writable_pages_sparc
#define eq128 eq128_sparc
@ -1608,6 +1609,29 @@
#define helper_get_cp_reg64 helper_get_cp_reg64_sparc
#define helper_get_r13_banked helper_get_r13_banked_sparc
#define helper_get_user_reg helper_get_user_reg_sparc
#define helper_gvec_add8 helper_gvec_add8_sparc
#define helper_gvec_add16 helper_gvec_add16_sparc
#define helper_gvec_add32 helper_gvec_add32_sparc
#define helper_gvec_add64 helper_gvec_add64_sparc
#define helper_gvec_and helper_gvec_and_sparc
#define helper_gvec_andc helper_gvec_andc_sparc
#define helper_gvec_dup8 helper_gvec_dup8_sparc
#define helper_gvec_dup16 helper_gvec_dup16_sparc
#define helper_gvec_dup32 helper_gvec_dup32_sparc
#define helper_gvec_dup64 helper_gvec_dup64_sparc
#define helper_gvec_mov helper_gvec_mov_sparc
#define helper_gvec_neg8 helper_gvec_neg8_sparc
#define helper_gvec_neg16 helper_gvec_neg16_sparc
#define helper_gvec_neg32 helper_gvec_neg32_sparc
#define helper_gvec_neg64 helper_gvec_neg64_sparc
#define helper_gvec_not helper_gvec_not_sparc
#define helper_gvec_or helper_gvec_or_sparc
#define helper_gvec_orc helper_gvec_orc_sparc
#define helper_gvec_sub8 helper_gvec_sub8_sparc
#define helper_gvec_sub16 helper_gvec_sub16_sparc
#define helper_gvec_sub32 helper_gvec_sub32_sparc
#define helper_gvec_sub64 helper_gvec_sub64_sparc
#define helper_gvec_xor helper_gvec_xor_sparc
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_sparc
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_sparc
#define helper_iwmmxt_addcw helper_iwmmxt_addcw_sparc
@ -2830,6 +2854,7 @@
#define shifter_out_im shifter_out_im_sparc
#define shortShift128Left shortShift128Left_sparc
#define shortShift192Left shortShift192Left_sparc
#define simd_desc simd_desc_sparc
#define simple_mpu_ap_bits simple_mpu_ap_bits_sparc
#define size_code_gen_buffer size_code_gen_buffer_sparc
#define softmmu_lock_user softmmu_lock_user_sparc
@ -2985,6 +3010,7 @@
#define tcg_enabled tcg_enabled_sparc
#define tcg_exec_all tcg_exec_all_sparc
#define tcg_exec_init tcg_exec_init_sparc
#define tcg_expand_vec_op tcg_expand_vec_op_sparc
#define tcg_find_helper tcg_find_helper_sparc
#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_sparc
#define tcg_func_start tcg_func_start_sparc
@ -3062,6 +3088,7 @@
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_sparc
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_sparc
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_sparc
#define tcg_gen_dupi_vec tcg_gen_dupi_vec_sparc
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_sparc
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_sparc
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_sparc
@ -3086,6 +3113,33 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_sparc
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_sparc
#define tcg_gen_goto_tb tcg_gen_goto_tb_sparc
#define tcg_gen_gvec_2 tcg_gen_gvec_2_sparc
#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_sparc
#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_sparc
#define tcg_gen_gvec_3 tcg_gen_gvec_3_sparc
#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_sparc
#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_sparc
#define tcg_gen_gvec_4 tcg_gen_gvec_4_sparc
#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_sparc
#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_sparc
#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_sparc
#define tcg_gen_gvec_add tcg_gen_gvec_add_sparc
#define tcg_gen_gvec_and tcg_gen_gvec_and_sparc
#define tcg_gen_gvec_andc tcg_gen_gvec_andc_sparc
#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_sparc
#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_sparc
#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_sparc
#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_sparc
#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_sparc
#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_sparc
#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_sparc
#define tcg_gen_gvec_mov tcg_gen_gvec_mov_sparc
#define tcg_gen_gvec_neg tcg_gen_gvec_neg_sparc
#define tcg_gen_gvec_not tcg_gen_gvec_not_sparc
#define tcg_gen_gvec_or tcg_gen_gvec_or_sparc
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_sparc
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_sparc
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_sparc
#define tcg_gen_insn_start tcg_gen_insn_start_sparc
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_sparc
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_sparc
@ -3205,6 +3259,15 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_sparc
#define tcg_gen_subi_i32 tcg_gen_subi_i32_sparc
#define tcg_gen_subi_i64 tcg_gen_subi_i64_sparc
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_sparc
#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_sparc
#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_sparc
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_sparc
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_sparc
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_sparc
#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_sparc
#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_sparc
#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_sparc
#define tcg_gen_xor_i32 tcg_gen_xor_i32_sparc
#define tcg_gen_xor_i64 tcg_gen_xor_i64_sparc
#define tcg_gen_xor_vec tcg_gen_xor_vec_sparc

63
qemu/sparc64.h
View file

@ -401,6 +401,7 @@
#define dummy_c15_cp_reginfo dummy_c15_cp_reginfo_sparc64
#define dummy_func dummy_func_sparc64
#define dummy_section dummy_section_sparc64
#define dup_const_impl dup_const_impl_sparc64
#define end_list end_list_sparc64
#define ensure_writable_pages ensure_writable_pages_sparc64
#define eq128 eq128_sparc64
@ -1608,6 +1609,29 @@
#define helper_get_cp_reg64 helper_get_cp_reg64_sparc64
#define helper_get_r13_banked helper_get_r13_banked_sparc64
#define helper_get_user_reg helper_get_user_reg_sparc64
#define helper_gvec_add8 helper_gvec_add8_sparc64
#define helper_gvec_add16 helper_gvec_add16_sparc64
#define helper_gvec_add32 helper_gvec_add32_sparc64
#define helper_gvec_add64 helper_gvec_add64_sparc64
#define helper_gvec_and helper_gvec_and_sparc64
#define helper_gvec_andc helper_gvec_andc_sparc64
#define helper_gvec_dup8 helper_gvec_dup8_sparc64
#define helper_gvec_dup16 helper_gvec_dup16_sparc64
#define helper_gvec_dup32 helper_gvec_dup32_sparc64
#define helper_gvec_dup64 helper_gvec_dup64_sparc64
#define helper_gvec_mov helper_gvec_mov_sparc64
#define helper_gvec_neg8 helper_gvec_neg8_sparc64
#define helper_gvec_neg16 helper_gvec_neg16_sparc64
#define helper_gvec_neg32 helper_gvec_neg32_sparc64
#define helper_gvec_neg64 helper_gvec_neg64_sparc64
#define helper_gvec_not helper_gvec_not_sparc64
#define helper_gvec_or helper_gvec_or_sparc64
#define helper_gvec_orc helper_gvec_orc_sparc64
#define helper_gvec_sub8 helper_gvec_sub8_sparc64
#define helper_gvec_sub16 helper_gvec_sub16_sparc64
#define helper_gvec_sub32 helper_gvec_sub32_sparc64
#define helper_gvec_sub64 helper_gvec_sub64_sparc64
#define helper_gvec_xor helper_gvec_xor_sparc64
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_sparc64
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_sparc64
#define helper_iwmmxt_addcw helper_iwmmxt_addcw_sparc64
@ -2830,6 +2854,7 @@
#define shifter_out_im shifter_out_im_sparc64
#define shortShift128Left shortShift128Left_sparc64
#define shortShift192Left shortShift192Left_sparc64
#define simd_desc simd_desc_sparc64
#define simple_mpu_ap_bits simple_mpu_ap_bits_sparc64
#define size_code_gen_buffer size_code_gen_buffer_sparc64
#define softmmu_lock_user softmmu_lock_user_sparc64
@ -2985,6 +3010,7 @@
#define tcg_enabled tcg_enabled_sparc64
#define tcg_exec_all tcg_exec_all_sparc64
#define tcg_exec_init tcg_exec_init_sparc64
#define tcg_expand_vec_op tcg_expand_vec_op_sparc64
#define tcg_find_helper tcg_find_helper_sparc64
#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_sparc64
#define tcg_func_start tcg_func_start_sparc64
@ -3062,6 +3088,7 @@
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_sparc64
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_sparc64
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_sparc64
#define tcg_gen_dupi_vec tcg_gen_dupi_vec_sparc64
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_sparc64
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_sparc64
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_sparc64
@ -3086,6 +3113,33 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_sparc64
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_sparc64
#define tcg_gen_goto_tb tcg_gen_goto_tb_sparc64
#define tcg_gen_gvec_2 tcg_gen_gvec_2_sparc64
#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_sparc64
#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_sparc64
#define tcg_gen_gvec_3 tcg_gen_gvec_3_sparc64
#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_sparc64
#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_sparc64
#define tcg_gen_gvec_4 tcg_gen_gvec_4_sparc64
#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_sparc64
#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_sparc64
#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_sparc64
#define tcg_gen_gvec_add tcg_gen_gvec_add_sparc64
#define tcg_gen_gvec_and tcg_gen_gvec_and_sparc64
#define tcg_gen_gvec_andc tcg_gen_gvec_andc_sparc64
#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_sparc64
#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_sparc64
#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_sparc64
#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_sparc64
#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_sparc64
#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_sparc64
#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_sparc64
#define tcg_gen_gvec_mov tcg_gen_gvec_mov_sparc64
#define tcg_gen_gvec_neg tcg_gen_gvec_neg_sparc64
#define tcg_gen_gvec_not tcg_gen_gvec_not_sparc64
#define tcg_gen_gvec_or tcg_gen_gvec_or_sparc64
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_sparc64
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_sparc64
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_sparc64
#define tcg_gen_insn_start tcg_gen_insn_start_sparc64
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_sparc64
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_sparc64
@ -3205,6 +3259,15 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_sparc64
#define tcg_gen_subi_i32 tcg_gen_subi_i32_sparc64
#define tcg_gen_subi_i64 tcg_gen_subi_i64_sparc64
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_sparc64
#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_sparc64
#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_sparc64
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_sparc64
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_sparc64
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_sparc64
#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_sparc64
#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_sparc64
#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_sparc64
#define tcg_gen_xor_i32 tcg_gen_xor_i32_sparc64
#define tcg_gen_xor_i64 tcg_gen_xor_i64_sparc64
#define tcg_gen_xor_vec tcg_gen_xor_vec_sparc64

325
qemu/tcg-runtime-gvec.c Normal file
View file

@ -0,0 +1,325 @@
/*
* Generic vectorized operation runtime
*
* Copyright (c) 2018 Linaro
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "qemu/host-utils.h"
#include "cpu.h"
#include "exec/helper-proto.h"
#include "tcg-gvec-desc.h"
/* Virtually all hosts support 16-byte vectors. Those that don't can emulate
* them via GCC's generic vector extension. This turns out to be simpler and
* more reliable than getting the compiler to autovectorize.
*
* In tcg-op-gvec.c, we asserted that both the size and alignment of the data
* are multiples of 16.
*
* When the compiler does not support all of the operations we require, the
* loops are written so that we can always fall back on the base types.
*/
#ifdef CONFIG_VECTOR16
typedef uint8_t vec8 __attribute__((vector_size(16)));
typedef uint16_t vec16 __attribute__((vector_size(16)));
typedef uint32_t vec32 __attribute__((vector_size(16)));
typedef uint64_t vec64 __attribute__((vector_size(16)));
typedef int8_t svec8 __attribute__((vector_size(16)));
typedef int16_t svec16 __attribute__((vector_size(16)));
typedef int32_t svec32 __attribute__((vector_size(16)));
typedef int64_t svec64 __attribute__((vector_size(16)));
#define DUP16(X) { X, X, X, X, X, X, X, X, X, X, X, X, X, X, X, X }
#define DUP8(X) { X, X, X, X, X, X, X, X }
#define DUP4(X) { X, X, X, X }
#define DUP2(X) { X, X }
#else
typedef uint8_t vec8;
typedef uint16_t vec16;
typedef uint32_t vec32;
typedef uint64_t vec64;
typedef int8_t svec8;
typedef int16_t svec16;
typedef int32_t svec32;
typedef int64_t svec64;
#define DUP16(X) X
#define DUP8(X) X
#define DUP4(X) X
#define DUP2(X) X
#endif /* CONFIG_VECTOR16 */
static inline void clear_high(void *d, intptr_t oprsz, uint32_t desc)
{
intptr_t maxsz = simd_maxsz(desc);
intptr_t i;
if (unlikely(maxsz > oprsz)) {
for (i = oprsz; i < maxsz; i += sizeof(uint64_t)) {
*(uint64_t *)(d + i) = 0;
}
}
}
void HELPER(gvec_add8)(void *d, void *a, void *b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(vec8)) {
*(vec8 *)(d + i) = *(vec8 *)(a + i) + *(vec8 *)(b + i);
}
clear_high(d, oprsz, desc);
}
void HELPER(gvec_add16)(void *d, void *a, void *b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(vec16)) {
*(vec16 *)(d + i) = *(vec16 *)(a + i) + *(vec16 *)(b + i);
}
clear_high(d, oprsz, desc);
}
void HELPER(gvec_add32)(void *d, void *a, void *b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(vec32)) {
*(vec32 *)(d + i) = *(vec32 *)(a + i) + *(vec32 *)(b + i);
}
clear_high(d, oprsz, desc);
}
void HELPER(gvec_add64)(void *d, void *a, void *b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(vec64)) {
*(vec64 *)(d + i) = *(vec64 *)(a + i) + *(vec64 *)(b + i);
}
clear_high(d, oprsz, desc);
}
void HELPER(gvec_sub8)(void *d, void *a, void *b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(vec8)) {
*(vec8 *)(d + i) = *(vec8 *)(a + i) - *(vec8 *)(b + i);
}
clear_high(d, oprsz, desc);
}
void HELPER(gvec_sub16)(void *d, void *a, void *b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(vec16)) {
*(vec16 *)(d + i) = *(vec16 *)(a + i) - *(vec16 *)(b + i);
}
clear_high(d, oprsz, desc);
}
void HELPER(gvec_sub32)(void *d, void *a, void *b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(vec32)) {
*(vec32 *)(d + i) = *(vec32 *)(a + i) - *(vec32 *)(b + i);
}
clear_high(d, oprsz, desc);
}
void HELPER(gvec_sub64)(void *d, void *a, void *b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(vec64)) {
*(vec64 *)(d + i) = *(vec64 *)(a + i) - *(vec64 *)(b + i);
}
clear_high(d, oprsz, desc);
}
void HELPER(gvec_neg8)(void *d, void *a, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(vec8)) {
*(vec8 *)(d + i) = -*(vec8 *)(a + i);
}
clear_high(d, oprsz, desc);
}
void HELPER(gvec_neg16)(void *d, void *a, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(vec16)) {
*(vec16 *)(d + i) = -*(vec16 *)(a + i);
}
clear_high(d, oprsz, desc);
}
void HELPER(gvec_neg32)(void *d, void *a, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(vec32)) {
*(vec32 *)(d + i) = -*(vec32 *)(a + i);
}
clear_high(d, oprsz, desc);
}
void HELPER(gvec_neg64)(void *d, void *a, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(vec64)) {
*(vec64 *)(d + i) = -*(vec64 *)(a + i);
}
clear_high(d, oprsz, desc);
}
void HELPER(gvec_mov)(void *d, void *a, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
memcpy(d, a, oprsz);
clear_high(d, oprsz, desc);
}
void HELPER(gvec_dup64)(void *d, uint32_t desc, uint64_t c)
{
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
if (c == 0) {
oprsz = 0;
} else {
for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
*(uint64_t *)(d + i) = c;
}
}
clear_high(d, oprsz, desc);
}
void HELPER(gvec_dup32)(void *d, uint32_t desc, uint32_t c)
{
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
if (c == 0) {
oprsz = 0;
} else {
for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
*(uint32_t *)(d + i) = c;
}
}
clear_high(d, oprsz, desc);
}
void HELPER(gvec_dup16)(void *d, uint32_t desc, uint32_t c)
{
HELPER(gvec_dup32)(d, desc, 0x00010001 * (c & 0xffff));
}
void HELPER(gvec_dup8)(void *d, uint32_t desc, uint32_t c)
{
HELPER(gvec_dup32)(d, desc, 0x01010101 * (c & 0xff));
}
void HELPER(gvec_not)(void *d, void *a, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(vec64)) {
*(vec64 *)(d + i) = ~*(vec64 *)(a + i);
}
clear_high(d, oprsz, desc);
}
void HELPER(gvec_and)(void *d, void *a, void *b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(vec64)) {
*(vec64 *)(d + i) = *(vec64 *)(a + i) & *(vec64 *)(b + i);
}
clear_high(d, oprsz, desc);
}
void HELPER(gvec_or)(void *d, void *a, void *b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(vec64)) {
*(vec64 *)(d + i) = *(vec64 *)(a + i) | *(vec64 *)(b + i);
}
clear_high(d, oprsz, desc);
}
void HELPER(gvec_xor)(void *d, void *a, void *b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(vec64)) {
*(vec64 *)(d + i) = *(vec64 *)(a + i) ^ *(vec64 *)(b + i);
}
clear_high(d, oprsz, desc);
}
void HELPER(gvec_andc)(void *d, void *a, void *b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(vec64)) {
*(vec64 *)(d + i) = *(vec64 *)(a + i) &~ *(vec64 *)(b + i);
}
clear_high(d, oprsz, desc);
}
void HELPER(gvec_orc)(void *d, void *a, void *b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(vec64)) {
*(vec64 *)(d + i) = *(vec64 *)(a + i) |~ *(vec64 *)(b + i);
}
clear_high(d, oprsz, desc);
}

49
qemu/tcg/tcg-gvec-desc.h Normal file
View file

@ -0,0 +1,49 @@
/*
* Generic vector operation descriptor
*
* Copyright (c) 2018 Linaro
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
/* ??? These bit widths are set for ARM SVE, maxing out at 256 byte vectors. */
#define SIMD_OPRSZ_SHIFT 0
#define SIMD_OPRSZ_BITS 5
#define SIMD_MAXSZ_SHIFT (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS)
#define SIMD_MAXSZ_BITS 5
#define SIMD_DATA_SHIFT (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS)
#define SIMD_DATA_BITS (32 - SIMD_DATA_SHIFT)
/* Create a descriptor from components. */
uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data);
/* Extract the operation size from a descriptor. */
static inline intptr_t simd_oprsz(uint32_t desc)
{
return (extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS) + 1) * 8;
}
/* Extract the max vector size from a descriptor. */
static inline intptr_t simd_maxsz(uint32_t desc)
{
return (extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) + 1) * 8;
}
/* Extract the operation-specific data from a descriptor. */
static inline int32_t simd_data(uint32_t desc)
{
return sextract32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS);
}

1309
qemu/tcg/tcg-op-gvec.c Normal file
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File diff suppressed because it is too large Load diff

198
qemu/tcg/tcg-op-gvec.h Normal file
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@ -0,0 +1,198 @@
/*
* Generic vector operation expansion
*
* Copyright (c) 2018 Linaro
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
/*
* "Generic" vectors. All operands are given as offsets from ENV,
* and therefore cannot also be allocated via tcg_global_mem_new_*.
* OPRSZ is the byte size of the vector upon which the operation is performed.
* MAXSZ is the byte size of the full vector; bytes beyond OPSZ are cleared.
*
* All sizes must be 8 or any multiple of 16.
* When OPRSZ is 8, the alignment may be 8, otherwise must be 16.
* Operands may completely, but not partially, overlap.
*/
/* Expand a call to a gvec-style helper, with pointers to two vector
operands, and a descriptor (see tcg-gvec-desc.h). */
typedef void gen_helper_gvec_2(TCGContext *s, TCGv_ptr, TCGv_ptr, TCGv_i32);
void tcg_gen_gvec_2_ool(TCGContext *, uint32_t dofs, uint32_t aofs,
uint32_t oprsz, uint32_t maxsz, int32_t data,
gen_helper_gvec_2 *fn);
/* Similarly, passing an extra pointer (e.g. env or float_status). */
typedef void gen_helper_gvec_2_ptr(TCGContext *s, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
void tcg_gen_gvec_2_ptr(TCGContext *, uint32_t dofs, uint32_t aofs,
TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
int32_t data, gen_helper_gvec_2_ptr *fn);
/* Similarly, with three vector operands. */
typedef void gen_helper_gvec_3(TCGContext *s, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
void tcg_gen_gvec_3_ool(TCGContext *, uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t oprsz, uint32_t maxsz, int32_t data,
gen_helper_gvec_3 *fn);
/* Similarly, with four vector operands. */
typedef void gen_helper_gvec_4(TCGContext *s, TCGv_ptr, TCGv_ptr, TCGv_ptr,
TCGv_ptr, TCGv_i32);
void tcg_gen_gvec_4_ool(TCGContext *, uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t cofs, uint32_t oprsz, uint32_t maxsz,
int32_t data, gen_helper_gvec_4 *fn);
/* Similarly, with five vector operands. */
typedef void gen_helper_gvec_5(TCGContext *s, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
TCGv_ptr, TCGv_i32);
void tcg_gen_gvec_5_ool(TCGContext *, uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t cofs, uint32_t xofs, uint32_t oprsz,
uint32_t maxsz, int32_t data, gen_helper_gvec_5 *fn);
typedef void gen_helper_gvec_3_ptr(TCGContext *s, TCGv_ptr, TCGv_ptr, TCGv_ptr,
TCGv_ptr, TCGv_i32);
void tcg_gen_gvec_3_ptr(TCGContext *, uint32_t dofs, uint32_t aofs, uint32_t bofs,
TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
int32_t data, gen_helper_gvec_3_ptr *fn);
typedef void gen_helper_gvec_4_ptr(TCGContext *s, TCGv_ptr, TCGv_ptr, TCGv_ptr,
TCGv_ptr, TCGv_ptr, TCGv_i32);
void tcg_gen_gvec_4_ptr(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t cofs, TCGv_ptr ptr, uint32_t oprsz,
uint32_t maxsz, int32_t data,
gen_helper_gvec_4_ptr *fn);
/* Expand a gvec operation. Either inline or out-of-line depending on
the actual vector size and the operations supported by the host. */
typedef struct {
/* Expand inline as a 64-bit or 32-bit integer.
Only one of these will be non-NULL. */
void (*fni8)(TCGContext *, TCGv_i64, TCGv_i64);
void (*fni4)(TCGContext *, TCGv_i32, TCGv_i32);
/* Expand inline with a host vector type. */
void (*fniv)(TCGContext *s, unsigned, TCGv_vec, TCGv_vec);
/* Expand out-of-line helper w/descriptor. */
gen_helper_gvec_2 *fno;
/* The opcode, if any, to which this corresponds. */
TCGOpcode opc;
/* The data argument to the out-of-line helper. */
int32_t data;
/* The vector element size, if applicable. */
uint8_t vece;
/* Prefer i64 to v64. */
bool prefer_i64;
} GVecGen2;
typedef struct {
/* Expand inline as a 64-bit or 32-bit integer.
Only one of these will be non-NULL. */
void (*fni8)(TCGContext *s, TCGv_i64, TCGv_i64, TCGv_i64);
void (*fni4)(TCGContext *s, TCGv_i32, TCGv_i32, TCGv_i32);
/* Expand inline with a host vector type. */
void (*fniv)(TCGContext *s, unsigned, TCGv_vec, TCGv_vec, TCGv_vec);
/* Expand out-of-line helper w/descriptor. */
gen_helper_gvec_3 *fno;
/* The opcode, if any, to which this corresponds. */
TCGOpcode opc;
/* The data argument to the out-of-line helper. */
int32_t data;
/* The vector element size, if applicable. */
uint8_t vece;
/* Prefer i64 to v64. */
bool prefer_i64;
/* Load dest as a 3rd source operand. */
bool load_dest;
} GVecGen3;
typedef struct {
/* Expand inline as a 64-bit or 32-bit integer.
Only one of these will be non-NULL. */
void (*fni8)(TCGContext *s, TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64);
void (*fni4)(TCGContext *s, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32);
/* Expand inline with a host vector type. */
void (*fniv)(TCGContext *s, unsigned, TCGv_vec, TCGv_vec, TCGv_vec, TCGv_vec);
/* Expand out-of-line helper w/descriptor. */
gen_helper_gvec_4 *fno;
/* The opcode, if any, to which this corresponds. */
TCGOpcode opc;
/* The data argument to the out-of-line helper. */
int32_t data;
/* The vector element size, if applicable. */
uint8_t vece;
/* Prefer i64 to v64. */
bool prefer_i64;
} GVecGen4;
void tcg_gen_gvec_2(TCGContext *, uint32_t dofs, uint32_t aofs,
uint32_t oprsz, uint32_t maxsz, const GVecGen2 *);
void tcg_gen_gvec_3(TCGContext *, uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t oprsz, uint32_t maxsz, const GVecGen3 *);
void tcg_gen_gvec_4(TCGContext *, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
uint32_t oprsz, uint32_t maxsz, const GVecGen4 *);
/* Expand a specific vector operation. */
void tcg_gen_gvec_mov(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t oprsz, uint32_t maxsz);
void tcg_gen_gvec_not(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t oprsz, uint32_t maxsz);
void tcg_gen_gvec_neg(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t oprsz, uint32_t maxsz);
void tcg_gen_gvec_add(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
void tcg_gen_gvec_sub(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
void tcg_gen_gvec_and(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
void tcg_gen_gvec_or(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
void tcg_gen_gvec_xor(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
void tcg_gen_gvec_andc(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
void tcg_gen_gvec_orc(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
void tcg_gen_gvec_dup_mem(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t s, uint32_t m);
void tcg_gen_gvec_dup_i32(TCGContext *, unsigned vece, uint32_t dofs, uint32_t s,
uint32_t m, TCGv_i32);
void tcg_gen_gvec_dup_i64(TCGContext *, unsigned vece, uint32_t dofs, uint32_t s,
uint32_t m, TCGv_i64);
void tcg_gen_gvec_dup8i(TCGContext *, uint32_t dofs, uint32_t s, uint32_t m, uint8_t x);
void tcg_gen_gvec_dup16i(TCGContext *, uint32_t dofs, uint32_t s, uint32_t m, uint16_t x);
void tcg_gen_gvec_dup32i(TCGContext *, uint32_t dofs, uint32_t s, uint32_t m, uint32_t x);
void tcg_gen_gvec_dup64i(TCGContext *, uint32_t dofs, uint32_t s, uint32_t m, uint64_t x);
/*
* 64-bit vector operations. Use these when the register has been allocated
* with tcg_global_mem_new_i64, and so we cannot also address it via pointer.
* OPRSZ = MAXSZ = 8.
*/
void tcg_gen_vec_neg8_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a);
void tcg_gen_vec_neg16_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a);
void tcg_gen_vec_neg32_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a);
void tcg_gen_vec_add8_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
void tcg_gen_vec_add16_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
void tcg_gen_vec_add32_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
void tcg_gen_vec_sub8_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
void tcg_gen_vec_sub16_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
void tcg_gen_vec_sub32_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);

33
qemu/tcg/tcg-op-vec.c
View file

@ -73,7 +73,8 @@ static void vec_gen_op2(TCGContext *s, TCGOpcode opc, unsigned vece, TCGv_vec r,
TCGTemp *at = tcgv_vec_temp(s, a);
TCGType type = rt->base_type;
tcg_debug_assert(at->base_type == type);
/* Must enough inputs for the output. */
tcg_debug_assert(at->base_type >= type);
vec_gen_2(s, opc, type, vece, temp_arg(rt), temp_arg(at));
}
@ -85,8 +86,9 @@ static void vec_gen_op3(TCGContext *s, TCGOpcode opc, unsigned vece,
TCGTemp *bt = tcgv_vec_temp(s, b);
TCGType type = rt->base_type;
tcg_debug_assert(at->base_type == type);
tcg_debug_assert(bt->base_type == type);
/* Must enough inputs for the output. */
tcg_debug_assert(at->base_type >= type);
tcg_debug_assert(bt->base_type >= type);
vec_gen_3(s, opc, type, vece, temp_arg(rt), temp_arg(at), temp_arg(bt));
}
@ -99,7 +101,7 @@ void tcg_gen_mov_vec(TCGContext *s, TCGv_vec r, TCGv_vec a)
#define MO_REG (TCG_TARGET_REG_BITS == 64 ? MO_64 : MO_32)
static void tcg_gen_dupi_vec(TCGContext *s, TCGv_vec r, unsigned vece, TCGArg a)
static void do_dupi_vec(TCGContext *s, TCGv_vec r, unsigned vece, TCGArg a)
{
TCGTemp *rt = tcgv_vec_temp(s, r);
vec_gen_2(s, INDEX_op_dupi_vec, rt->base_type, vece, temp_arg(rt), a);
@ -108,14 +110,14 @@ static void tcg_gen_dupi_vec(TCGContext *s, TCGv_vec r, unsigned vece, TCGArg a)
TCGv_vec tcg_const_zeros_vec(TCGContext *s, TCGType type)
{
TCGv_vec ret = tcg_temp_new_vec(s, type);
tcg_gen_dupi_vec(s, ret, MO_REG, 0);
do_dupi_vec(s, ret, MO_REG, 0);
return ret;
}
TCGv_vec tcg_const_ones_vec(TCGContext *s, TCGType type)
{
TCGv_vec ret = tcg_temp_new_vec(s, type);
tcg_gen_dupi_vec(s, ret, MO_REG, -1);
do_dupi_vec(s, ret, MO_REG, -1);
return ret;
}
@ -134,9 +136,9 @@ TCGv_vec tcg_const_ones_vec_matching(TCGContext *s, TCGv_vec m)
void tcg_gen_dup64i_vec(TCGContext *s, TCGv_vec r, uint64_t a)
{
if (TCG_TARGET_REG_BITS == 32 && a == deposit64(a, 32, 32, a)) {
tcg_gen_dupi_vec(s, r, MO_32, a);
do_dupi_vec(s, r, MO_32, a);
} else if (TCG_TARGET_REG_BITS == 64 || a == (uint64_t)(int32_t)a) {
tcg_gen_dupi_vec(s, r, MO_64, a);
do_dupi_vec(s, r, MO_64, a);
} else {
TCGv_i64 c = tcg_const_i64(s, a);
tcg_gen_dup_i64_vec(s, MO_64, r, c);
@ -146,17 +148,22 @@ void tcg_gen_dup64i_vec(TCGContext *s, TCGv_vec r, uint64_t a)
void tcg_gen_dup32i_vec(TCGContext *s, TCGv_vec r, uint32_t a)
{
tcg_gen_dupi_vec(s, r, MO_REG, ((TCGArg)-1 / 0xffffffffu) * a);
do_dupi_vec(s, r, MO_REG, dup_const(MO_32, a));
}
void tcg_gen_dup16i_vec(TCGContext *s, TCGv_vec r, uint32_t a)
{
tcg_gen_dupi_vec(s, r, MO_REG, ((TCGArg)-1 / 0xffff) * (a & 0xffff));
do_dupi_vec(s, r, MO_REG, dup_const(MO_16, a));
}
void tcg_gen_dup8i_vec(TCGContext *s, TCGv_vec r, uint32_t a)
{
tcg_gen_dupi_vec(s, r, MO_REG, ((TCGArg)-1 / 0xff) * (a & 0xff));
do_dupi_vec(s, r, MO_REG, dup_const(MO_8, a));
}
void tcg_gen_dupi_vec(TCGContext *s, unsigned vece, TCGv_vec r, uint64_t a)
{
do_dupi_vec(s, r, MO_REG, dup_const(vece, a));
}
void tcg_gen_dup_i64_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_i64 a)
@ -167,14 +174,14 @@ void tcg_gen_dup_i64_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_i64 a)
if (TCG_TARGET_REG_BITS == 64) {
TCGArg ai = tcgv_i64_arg(s, a);
vec_gen_2(s, INDEX_op_dup_vec, type, MO_64, ri, ai);
vec_gen_2(s, INDEX_op_dup_vec, type, vece, ri, ai);
} else if (vece == MO_64) {
TCGArg al = tcgv_i32_arg(s, TCGV_LOW(s, a));
TCGArg ah = tcgv_i32_arg(s, TCGV_HIGH(s, a));
vec_gen_3(s, INDEX_op_dup2_vec, type, MO_64, ri, al, ah);
} else {
TCGArg ai = tcgv_i32_arg(s, TCGV_LOW(s, a));
vec_gen_2(s, INDEX_op_dup_vec, type, MO_64, ri, ai);
vec_gen_2(s, INDEX_op_dup_vec, type, vece, ri, ai);
}
}

1
qemu/tcg/tcg-op.h
View file

@ -922,6 +922,7 @@ void tcg_gen_dup8i_vec(TCGContext *, TCGv_vec, uint32_t);
void tcg_gen_dup16i_vec(TCGContext *, TCGv_vec, uint32_t);
void tcg_gen_dup32i_vec(TCGContext *, TCGv_vec, uint32_t);
void tcg_gen_dup64i_vec(TCGContext *, TCGv_vec, uint64_t);
void tcg_gen_dupi_vec(TCGContext *, unsigned vece, TCGv_vec, uint64_t);
void tcg_gen_add_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_sub_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_and_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);

6
qemu/tcg/tcg-opc.h
View file

@ -232,6 +232,12 @@ DEF(andc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_andc_vec))
DEF(orc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_orc_vec))
DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec))
DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)
#if TCG_TARGET_MAYBE_vec
#include "tcg-target.opc.h"
#endif
#undef TLADDR_ARGS
#undef DATA64_ARGS
#undef IMPL

30
qemu/tcg/tcg-runtime.h
View file

@ -135,3 +135,33 @@ GEN_ATOMIC_HELPERS(xor_fetch)
GEN_ATOMIC_HELPERS(xchg)
#undef GEN_ATOMIC_HELPERS
DEF_HELPER_FLAGS_3(gvec_mov, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(gvec_dup8, TCG_CALL_NO_RWG, void, ptr, i32, i32)
DEF_HELPER_FLAGS_3(gvec_dup16, TCG_CALL_NO_RWG, void, ptr, i32, i32)
DEF_HELPER_FLAGS_3(gvec_dup32, TCG_CALL_NO_RWG, void, ptr, i32, i32)
DEF_HELPER_FLAGS_3(gvec_dup64, TCG_CALL_NO_RWG, void, ptr, i32, i64)
DEF_HELPER_FLAGS_4(gvec_add8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_add16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_add32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_add64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_sub8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_sub16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_sub32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_sub64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(gvec_neg8, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(gvec_neg16, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(gvec_neg32, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(gvec_neg64, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(gvec_not, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_and, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_or, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_xor, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_andc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_orc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

13
qemu/tcg/tcg.c
View file

@ -1060,10 +1060,10 @@ bool tcg_op_supported(TCGOpcode op)
case INDEX_op_orc_vec:
return have_vec && TCG_TARGET_HAS_orc_vec;
case NB_OPS:
break;
default:
tcg_debug_assert(op > INDEX_op_last_generic && op < NB_OPS);
return true;
}
g_assert_not_reached();
}
/* Note: we convert the 64 bit args to 32 bit and do some alignment
@ -3129,3 +3129,10 @@ void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf)
cpu_fprintf(f, "[TCG profiler not compiled]\n");
}
#endif
#if !TCG_TARGET_MAYBE_vec
void tcg_expand_vec_op(TCGOpcode o, TCGType t, unsigned e, TCGArg a0, ...)
{
g_assert_not_reached();
}
#endif

29
qemu/tcg/tcg.h
View file

@ -1094,7 +1094,7 @@ static inline TCGv_i64 tcg_temp_local_new_i64(TCGContext *s)
}
// UNICORN: Added
#define TCG_OP_DEFS_TABLE_SIZE 151
#define TCG_OP_DEFS_TABLE_SIZE 152
extern const TCGOpDef tcg_op_defs_org[TCG_OP_DEFS_TABLE_SIZE];
typedef struct TCGTargetOpDef {
@ -1339,6 +1339,33 @@ static inline unsigned get_mmuidx(TCGMemOpIdx oi)
((uintptr_t (*)(void *, void *))tcg_ctx->code_gen_prologue)(env, tb_ptr)
#endif
#if TCG_TARGET_MAYBE_vec
/* Return zero if the tuple (opc, type, vece) is unsupportable;
return > 0 if it is directly supportable;
return < 0 if we must call tcg_expand_vec_op. */
int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned);
#else
static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve)
{
return 0;
}
#endif
/* Expand the tuple (opc, type, vece) on the given arguments. */
void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...);
/* Replicate a constant C accoring to the log2 of the element size. */
// Unicorn: renamed to avoid symbol clashing
uint64_t dup_const_impl(unsigned vece, uint64_t c);
#define dup_const(VECE, C) \
(__builtin_constant_p(VECE) \
? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \
: (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \
: (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \
: dup_const_impl(VECE, C)) \
: dup_const_impl(VECE, C))
/*
* Memory helpers that will be used by TCG generated code.
*/

63
qemu/x86_64.h
View file

@ -401,6 +401,7 @@
#define dummy_c15_cp_reginfo dummy_c15_cp_reginfo_x86_64
#define dummy_func dummy_func_x86_64
#define dummy_section dummy_section_x86_64
#define dup_const_impl dup_const_impl_x86_64
#define end_list end_list_x86_64
#define ensure_writable_pages ensure_writable_pages_x86_64
#define eq128 eq128_x86_64
@ -1608,6 +1609,29 @@
#define helper_get_cp_reg64 helper_get_cp_reg64_x86_64
#define helper_get_r13_banked helper_get_r13_banked_x86_64
#define helper_get_user_reg helper_get_user_reg_x86_64
#define helper_gvec_add8 helper_gvec_add8_x86_64
#define helper_gvec_add16 helper_gvec_add16_x86_64
#define helper_gvec_add32 helper_gvec_add32_x86_64
#define helper_gvec_add64 helper_gvec_add64_x86_64
#define helper_gvec_and helper_gvec_and_x86_64
#define helper_gvec_andc helper_gvec_andc_x86_64
#define helper_gvec_dup8 helper_gvec_dup8_x86_64
#define helper_gvec_dup16 helper_gvec_dup16_x86_64
#define helper_gvec_dup32 helper_gvec_dup32_x86_64
#define helper_gvec_dup64 helper_gvec_dup64_x86_64
#define helper_gvec_mov helper_gvec_mov_x86_64
#define helper_gvec_neg8 helper_gvec_neg8_x86_64
#define helper_gvec_neg16 helper_gvec_neg16_x86_64
#define helper_gvec_neg32 helper_gvec_neg32_x86_64
#define helper_gvec_neg64 helper_gvec_neg64_x86_64
#define helper_gvec_not helper_gvec_not_x86_64
#define helper_gvec_or helper_gvec_or_x86_64
#define helper_gvec_orc helper_gvec_orc_x86_64
#define helper_gvec_sub8 helper_gvec_sub8_x86_64
#define helper_gvec_sub16 helper_gvec_sub16_x86_64
#define helper_gvec_sub32 helper_gvec_sub32_x86_64
#define helper_gvec_sub64 helper_gvec_sub64_x86_64
#define helper_gvec_xor helper_gvec_xor_x86_64
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_x86_64
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_x86_64
#define helper_iwmmxt_addcw helper_iwmmxt_addcw_x86_64
@ -2830,6 +2854,7 @@
#define shifter_out_im shifter_out_im_x86_64
#define shortShift128Left shortShift128Left_x86_64
#define shortShift192Left shortShift192Left_x86_64
#define simd_desc simd_desc_x86_64
#define simple_mpu_ap_bits simple_mpu_ap_bits_x86_64
#define size_code_gen_buffer size_code_gen_buffer_x86_64
#define softmmu_lock_user softmmu_lock_user_x86_64
@ -2985,6 +3010,7 @@
#define tcg_enabled tcg_enabled_x86_64
#define tcg_exec_all tcg_exec_all_x86_64
#define tcg_exec_init tcg_exec_init_x86_64
#define tcg_expand_vec_op tcg_expand_vec_op_x86_64
#define tcg_find_helper tcg_find_helper_x86_64
#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_x86_64
#define tcg_func_start tcg_func_start_x86_64
@ -3062,6 +3088,7 @@
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_x86_64
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_x86_64
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_x86_64
#define tcg_gen_dupi_vec tcg_gen_dupi_vec_x86_64
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_x86_64
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_x86_64
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_x86_64
@ -3086,6 +3113,33 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_x86_64
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_x86_64
#define tcg_gen_goto_tb tcg_gen_goto_tb_x86_64
#define tcg_gen_gvec_2 tcg_gen_gvec_2_x86_64
#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_x86_64
#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_x86_64
#define tcg_gen_gvec_3 tcg_gen_gvec_3_x86_64
#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_x86_64
#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_x86_64
#define tcg_gen_gvec_4 tcg_gen_gvec_4_x86_64
#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_x86_64
#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_x86_64
#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_x86_64
#define tcg_gen_gvec_add tcg_gen_gvec_add_x86_64
#define tcg_gen_gvec_and tcg_gen_gvec_and_x86_64
#define tcg_gen_gvec_andc tcg_gen_gvec_andc_x86_64
#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_x86_64
#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_x86_64
#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_x86_64
#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_x86_64
#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_x86_64
#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_x86_64
#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_x86_64
#define tcg_gen_gvec_mov tcg_gen_gvec_mov_x86_64
#define tcg_gen_gvec_neg tcg_gen_gvec_neg_x86_64
#define tcg_gen_gvec_not tcg_gen_gvec_not_x86_64
#define tcg_gen_gvec_or tcg_gen_gvec_or_x86_64
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_x86_64
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_x86_64
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_x86_64
#define tcg_gen_insn_start tcg_gen_insn_start_x86_64
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_x86_64
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_x86_64
@ -3205,6 +3259,15 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_x86_64
#define tcg_gen_subi_i32 tcg_gen_subi_i32_x86_64
#define tcg_gen_subi_i64 tcg_gen_subi_i64_x86_64
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_x86_64
#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_x86_64
#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_x86_64
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_x86_64
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_x86_64
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_x86_64
#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_x86_64
#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_x86_64
#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_x86_64
#define tcg_gen_xor_i32 tcg_gen_xor_i32_x86_64
#define tcg_gen_xor_i64 tcg_gen_xor_i64_x86_64
#define tcg_gen_xor_vec tcg_gen_xor_vec_x86_64