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tcg/sparc: Add support for fence
Backports commit f8f03b3707b49898052fb8cd75ee31d19c8161fc from qemu
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a6fdc24e28
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@ -251,6 +251,8 @@ static const int tcg_target_call_oarg_regs[] = {
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#define STWA (INSN_OP(3) | INSN_OP3(0x14))
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#define STWA (INSN_OP(3) | INSN_OP3(0x14))
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#define STXA (INSN_OP(3) | INSN_OP3(0x1e))
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#define STXA (INSN_OP(3) | INSN_OP3(0x1e))
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#define MEMBAR (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(15) | (1 << 13))
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#ifndef ASI_PRIMARY_LITTLE
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#ifndef ASI_PRIMARY_LITTLE
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#define ASI_PRIMARY_LITTLE 0x88
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#define ASI_PRIMARY_LITTLE 0x88
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#endif
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#endif
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@ -837,6 +839,12 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest)
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tcg_out_nop(s);
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tcg_out_nop(s);
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}
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}
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static void tcg_out_mb(TCGContext *s, TCGArg a0)
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{
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/* Note that the TCG memory order constants mirror the Sparc MEMBAR. */
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tcg_out32(s, MEMBAR | (a0 & TCG_MO_ALL));
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}
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#ifdef CONFIG_SOFTMMU
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#ifdef CONFIG_SOFTMMU
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static tcg_insn_unit *qemu_ld_trampoline[16];
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static tcg_insn_unit *qemu_ld_trampoline[16];
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static tcg_insn_unit *qemu_st_trampoline[16];
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static tcg_insn_unit *qemu_st_trampoline[16];
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@ -1468,6 +1476,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c);
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tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c);
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break;
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break;
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case INDEX_op_mb:
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tcg_out_mb(s, a0);
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break;
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case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
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case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
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case INDEX_op_mov_i64:
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case INDEX_op_mov_i64:
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case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
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case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
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@ -1569,6 +1581,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
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{ INDEX_op_qemu_st_i32, { "sZ", "A" } },
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{ INDEX_op_qemu_st_i32, { "sZ", "A" } },
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{ INDEX_op_qemu_st_i64, { "SZ", "A" } },
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{ INDEX_op_qemu_st_i64, { "SZ", "A" } },
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{ INDEX_op_mb, { } },
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{ -1 },
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{ -1 },
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};
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};
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