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target/arm: implement SHA-3 instructions

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This implements emulation of the new SHA-3 instructions that have
been added as an optional extensions to the ARMv8 Crypto Extensions
in ARM v8.2.

Backports commit cd270ade74ea86467f393a9fb9c54c4f1148c28f from qemu
This commit is contained in:
Ard Biesheuvel 2018-03-07 08:41:34 -05:00 committed by Lioncash
parent 0ef74f6d6d
commit 66b8b01f09
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 26 additions and 4 deletions
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30
qemu/target/arm/translate-a64.c
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@ -11829,9 +11829,10 @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
feature = ARM_FEATURE_V8_SHA512; feature = ARM_FEATURE_V8_SHA512;
genfn = gen_helper_crypto_sha512su1; genfn = gen_helper_crypto_sha512su1;
break; break;
default: case 3: /* RAX1 */
unallocated_encoding(s); feature = ARM_FEATURE_V8_SHA3;
return; genfn = NULL;
break;
} }
} else { } else {
unallocated_encoding(s); unallocated_encoding(s);
@ -11860,7 +11861,28 @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
tcg_temp_free_ptr(tcg_ctx, tcg_rn_ptr); tcg_temp_free_ptr(tcg_ctx, tcg_rn_ptr);
tcg_temp_free_ptr(tcg_ctx, tcg_rm_ptr); tcg_temp_free_ptr(tcg_ctx, tcg_rm_ptr);
} else { } else {
g_assert_not_reached(); TCGv_i64 tcg_op1, tcg_op2, tcg_res[2];
int pass;
tcg_op1 = tcg_temp_new_i64(tcg_ctx);
tcg_op2 = tcg_temp_new_i64(tcg_ctx);
tcg_res[0] = tcg_temp_new_i64(tcg_ctx);
tcg_res[1] = tcg_temp_new_i64(tcg_ctx);
for (pass = 0; pass < 2; pass++) {
read_vec_element(s, tcg_op1, rn, pass, MO_64);
read_vec_element(s, tcg_op2, rm, pass, MO_64);
tcg_gen_rotli_i64(tcg_ctx, tcg_res[pass], tcg_op2, 1);
tcg_gen_xor_i64(tcg_ctx, tcg_res[pass], tcg_res[pass], tcg_op1);
}
write_vec_element(s, tcg_res[0], rd, 0, MO_64);
write_vec_element(s, tcg_res[1], rd, 1, MO_64);
tcg_temp_free_i64(tcg_ctx, tcg_op1);
tcg_temp_free_i64(tcg_ctx, tcg_op2);
tcg_temp_free_i64(tcg_ctx, tcg_res[0]);
tcg_temp_free_i64(tcg_ctx, tcg_res[1]);
} }
} }