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target/arm: Add mte helpers for sve scalar + int loads

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Because the elements are sequential, we can eliminate many tests all
at once when the tag hits TCMA, or if the page(s) are not Tagged.

Backports commit 206adacfb8d35e671e3619591608c475aa046b63 from qemu
This commit is contained in:
Richard Henderson 2021-02-25 21:43:39 -05:00 committed by Lioncash
parent 6a78133659
commit 670b25c5fa
8 changed files with 515 additions and 91 deletions
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46
qemu/aarch64.h
View file

@ -4153,6 +4153,52 @@
#define helper_sve_ldhsu_le_zss helper_sve_ldhsu_le_zss_aarch64
#define helper_sve_ldhsu_be_zsu helper_sve_ldhsu_be_zsu_aarch64
#define helper_sve_ldhsu_le_zsu helper_sve_ldhsu_le_zsu_aarch64
#define helper_sve_ld1bb_r_mte helper_sve_ld1bb_r_mte_aarch64
#define helper_sve_ld2bb_r_mte helper_sve_ld2bb_r_mte_aarch64
#define helper_sve_ld3bb_r_mte helper_sve_ld3bb_r_mte_aarch64
#define helper_sve_ld4bb_r_mte helper_sve_ld4bb_r_mte_aarch64
#define helper_sve_ld1hh_le_r_mte helper_sve_ld1hh_le_r_mte_aarch64
#define helper_sve_ld2hh_le_r_mte helper_sve_ld2hh_le_r_mte_aarch64
#define helper_sve_ld3hh_le_r_mte helper_sve_ld3hh_le_r_mte_aarch64
#define helper_sve_ld4hh_le_r_mte helper_sve_ld4hh_le_r_mte_aarch64
#define helper_sve_ld1hh_be_r_mte helper_sve_ld1hh_be_r_mte_aarch64
#define helper_sve_ld2hh_be_r_mte helper_sve_ld2hh_be_r_mte_aarch64
#define helper_sve_ld3hh_be_r_mte helper_sve_ld3hh_be_r_mte_aarch64
#define helper_sve_ld4hh_be_r_mte helper_sve_ld4hh_be_r_mte_aarch64
#define helper_sve_ld1ss_le_r_mte helper_sve_ld1ss_le_r_mte_aarch64
#define helper_sve_ld2ss_le_r_mte helper_sve_ld2ss_le_r_mte_aarch64
#define helper_sve_ld3ss_le_r_mte helper_sve_ld3ss_le_r_mte_aarch64
#define helper_sve_ld4ss_le_r_mte helper_sve_ld4ss_le_r_mte_aarch64
#define helper_sve_ld1ss_be_r_mte helper_sve_ld1ss_be_r_mte_aarch64
#define helper_sve_ld2ss_be_r_mte helper_sve_ld2ss_be_r_mte_aarch64
#define helper_sve_ld3ss_be_r_mte helper_sve_ld3ss_be_r_mte_aarch64
#define helper_sve_ld4ss_be_r_mte helper_sve_ld4ss_be_r_mte_aarch64
#define helper_sve_ld1dd_le_r_mte helper_sve_ld1dd_le_r_mte_aarch64
#define helper_sve_ld2dd_le_r_mte helper_sve_ld2dd_le_r_mte_aarch64
#define helper_sve_ld3dd_le_r_mte helper_sve_ld3dd_le_r_mte_aarch64
#define helper_sve_ld4dd_le_r_mte helper_sve_ld4dd_le_r_mte_aarch64
#define helper_sve_ld1dd_be_r_mte helper_sve_ld1dd_be_r_mte_aarch64
#define helper_sve_ld2dd_be_r_mte helper_sve_ld2dd_be_r_mte_aarch64
#define helper_sve_ld3dd_be_r_mte helper_sve_ld3dd_be_r_mte_aarch64
#define helper_sve_ld4dd_be_r_mte helper_sve_ld4dd_be_r_mte_aarch64
#define helper_sve_ld1bhu_r_mte helper_sve_ld1bhu_r_mte_aarch64
#define helper_sve_ld1bsu_r_mte helper_sve_ld1bsu_r_mte_aarch64
#define helper_sve_ld1bdu_r_mte helper_sve_ld1bdu_r_mte_aarch64
#define helper_sve_ld1bhs_r_mte helper_sve_ld1bhs_r_mte_aarch64
#define helper_sve_ld1bss_r_mte helper_sve_ld1bss_r_mte_aarch64
#define helper_sve_ld1bds_r_mte helper_sve_ld1bds_r_mte_aarch64
#define helper_sve_ld1hsu_le_r_mte helper_sve_ld1hsu_le_r_mte_aarch64
#define helper_sve_ld1hdu_le_r_mte helper_sve_ld1hdu_le_r_mte_aarch64
#define helper_sve_ld1hss_le_r_mte helper_sve_ld1hss_le_r_mte_aarch64
#define helper_sve_ld1hds_le_r_mte helper_sve_ld1hds_le_r_mte_aarch64
#define helper_sve_ld1hsu_be_r_mte helper_sve_ld1hsu_be_r_mte_aarch64
#define helper_sve_ld1hdu_be_r_mte helper_sve_ld1hdu_be_r_mte_aarch64
#define helper_sve_ld1hss_be_r_mte helper_sve_ld1hss_be_r_mte_aarch64
#define helper_sve_ld1hds_be_r_mte helper_sve_ld1hds_be_r_mte_aarch64
#define helper_sve_ld1sdu_le_r_mte helper_sve_ld1sdu_le_r_mte_aarch64
#define helper_sve_ld1sds_le_r_mte helper_sve_ld1sds_le_r_mte_aarch64
#define helper_sve_ld1sdu_be_r_mte helper_sve_ld1sdu_be_r_mte_aarch64
#define helper_sve_ld1sds_be_r_mte helper_sve_ld1sds_be_r_mte_aarch64
#define helper_sve_ldsds_be_zd helper_sve_ldsds_be_zd_aarch64
#define helper_sve_ldsds_le_zd helper_sve_ldsds_le_zd_aarch64
#define helper_sve_ldsds_be_zss helper_sve_ldsds_be_zss_aarch64

46
qemu/aarch64eb.h
View file

@ -4153,6 +4153,52 @@
#define helper_sve_ldhsu_le_zss helper_sve_ldhsu_le_zss_aarch64eb
#define helper_sve_ldhsu_be_zsu helper_sve_ldhsu_be_zsu_aarch64eb
#define helper_sve_ldhsu_le_zsu helper_sve_ldhsu_le_zsu_aarch64eb
#define helper_sve_ld1bb_r_mte helper_sve_ld1bb_r_mte_aarch64eb
#define helper_sve_ld2bb_r_mte helper_sve_ld2bb_r_mte_aarch64eb
#define helper_sve_ld3bb_r_mte helper_sve_ld3bb_r_mte_aarch64eb
#define helper_sve_ld4bb_r_mte helper_sve_ld4bb_r_mte_aarch64eb
#define helper_sve_ld1hh_le_r_mte helper_sve_ld1hh_le_r_mte_aarch64eb
#define helper_sve_ld2hh_le_r_mte helper_sve_ld2hh_le_r_mte_aarch64eb
#define helper_sve_ld3hh_le_r_mte helper_sve_ld3hh_le_r_mte_aarch64eb
#define helper_sve_ld4hh_le_r_mte helper_sve_ld4hh_le_r_mte_aarch64eb
#define helper_sve_ld1hh_be_r_mte helper_sve_ld1hh_be_r_mte_aarch64eb
#define helper_sve_ld2hh_be_r_mte helper_sve_ld2hh_be_r_mte_aarch64eb
#define helper_sve_ld3hh_be_r_mte helper_sve_ld3hh_be_r_mte_aarch64eb
#define helper_sve_ld4hh_be_r_mte helper_sve_ld4hh_be_r_mte_aarch64eb
#define helper_sve_ld1ss_le_r_mte helper_sve_ld1ss_le_r_mte_aarch64eb
#define helper_sve_ld2ss_le_r_mte helper_sve_ld2ss_le_r_mte_aarch64eb
#define helper_sve_ld3ss_le_r_mte helper_sve_ld3ss_le_r_mte_aarch64eb
#define helper_sve_ld4ss_le_r_mte helper_sve_ld4ss_le_r_mte_aarch64eb
#define helper_sve_ld1ss_be_r_mte helper_sve_ld1ss_be_r_mte_aarch64eb
#define helper_sve_ld2ss_be_r_mte helper_sve_ld2ss_be_r_mte_aarch64eb
#define helper_sve_ld3ss_be_r_mte helper_sve_ld3ss_be_r_mte_aarch64eb
#define helper_sve_ld4ss_be_r_mte helper_sve_ld4ss_be_r_mte_aarch64eb
#define helper_sve_ld1dd_le_r_mte helper_sve_ld1dd_le_r_mte_aarch64eb
#define helper_sve_ld2dd_le_r_mte helper_sve_ld2dd_le_r_mte_aarch64eb
#define helper_sve_ld3dd_le_r_mte helper_sve_ld3dd_le_r_mte_aarch64eb
#define helper_sve_ld4dd_le_r_mte helper_sve_ld4dd_le_r_mte_aarch64eb
#define helper_sve_ld1dd_be_r_mte helper_sve_ld1dd_be_r_mte_aarch64eb
#define helper_sve_ld2dd_be_r_mte helper_sve_ld2dd_be_r_mte_aarch64eb
#define helper_sve_ld3dd_be_r_mte helper_sve_ld3dd_be_r_mte_aarch64eb
#define helper_sve_ld4dd_be_r_mte helper_sve_ld4dd_be_r_mte_aarch64eb
#define helper_sve_ld1bhu_r_mte helper_sve_ld1bhu_r_mte_aarch64eb
#define helper_sve_ld1bsu_r_mte helper_sve_ld1bsu_r_mte_aarch64eb
#define helper_sve_ld1bdu_r_mte helper_sve_ld1bdu_r_mte_aarch64eb
#define helper_sve_ld1bhs_r_mte helper_sve_ld1bhs_r_mte_aarch64eb
#define helper_sve_ld1bss_r_mte helper_sve_ld1bss_r_mte_aarch64eb
#define helper_sve_ld1bds_r_mte helper_sve_ld1bds_r_mte_aarch64eb
#define helper_sve_ld1hsu_le_r_mte helper_sve_ld1hsu_le_r_mte_aarch64eb
#define helper_sve_ld1hdu_le_r_mte helper_sve_ld1hdu_le_r_mte_aarch64eb
#define helper_sve_ld1hss_le_r_mte helper_sve_ld1hss_le_r_mte_aarch64eb
#define helper_sve_ld1hds_le_r_mte helper_sve_ld1hds_le_r_mte_aarch64eb
#define helper_sve_ld1hsu_be_r_mte helper_sve_ld1hsu_be_r_mte_aarch64eb
#define helper_sve_ld1hdu_be_r_mte helper_sve_ld1hdu_be_r_mte_aarch64eb
#define helper_sve_ld1hss_be_r_mte helper_sve_ld1hss_be_r_mte_aarch64eb
#define helper_sve_ld1hds_be_r_mte helper_sve_ld1hds_be_r_mte_aarch64eb
#define helper_sve_ld1sdu_le_r_mte helper_sve_ld1sdu_le_r_mte_aarch64eb
#define helper_sve_ld1sds_le_r_mte helper_sve_ld1sds_le_r_mte_aarch64eb
#define helper_sve_ld1sdu_be_r_mte helper_sve_ld1sdu_be_r_mte_aarch64eb
#define helper_sve_ld1sds_be_r_mte helper_sve_ld1sds_be_r_mte_aarch64eb
#define helper_sve_ldsds_be_zd helper_sve_ldsds_be_zd_aarch64eb
#define helper_sve_ldsds_le_zd helper_sve_ldsds_le_zd_aarch64eb
#define helper_sve_ldsds_be_zss helper_sve_ldsds_be_zss_aarch64eb

46
qemu/header_gen.py
View file

@ -4293,6 +4293,52 @@ aarch64_symbols = (
'helper_sve_ldhsu_le_zss',
'helper_sve_ldhsu_be_zsu',
'helper_sve_ldhsu_le_zsu',
'helper_sve_ld1bb_r_mte',
'helper_sve_ld2bb_r_mte',
'helper_sve_ld3bb_r_mte',
'helper_sve_ld4bb_r_mte',
'helper_sve_ld1hh_le_r_mte',
'helper_sve_ld2hh_le_r_mte',
'helper_sve_ld3hh_le_r_mte',
'helper_sve_ld4hh_le_r_mte',
'helper_sve_ld1hh_be_r_mte',
'helper_sve_ld2hh_be_r_mte',
'helper_sve_ld3hh_be_r_mte',
'helper_sve_ld4hh_be_r_mte',
'helper_sve_ld1ss_le_r_mte',
'helper_sve_ld2ss_le_r_mte',
'helper_sve_ld3ss_le_r_mte',
'helper_sve_ld4ss_le_r_mte',
'helper_sve_ld1ss_be_r_mte',
'helper_sve_ld2ss_be_r_mte',
'helper_sve_ld3ss_be_r_mte',
'helper_sve_ld4ss_be_r_mte',
'helper_sve_ld1dd_le_r_mte',
'helper_sve_ld2dd_le_r_mte',
'helper_sve_ld3dd_le_r_mte',
'helper_sve_ld4dd_le_r_mte',
'helper_sve_ld1dd_be_r_mte',
'helper_sve_ld2dd_be_r_mte',
'helper_sve_ld3dd_be_r_mte',
'helper_sve_ld4dd_be_r_mte',
'helper_sve_ld1bhu_r_mte',
'helper_sve_ld1bsu_r_mte',
'helper_sve_ld1bdu_r_mte',
'helper_sve_ld1bhs_r_mte',
'helper_sve_ld1bss_r_mte',
'helper_sve_ld1bds_r_mte',
'helper_sve_ld1hsu_le_r_mte',
'helper_sve_ld1hdu_le_r_mte',
'helper_sve_ld1hss_le_r_mte',
'helper_sve_ld1hds_le_r_mte',
'helper_sve_ld1hsu_be_r_mte',
'helper_sve_ld1hdu_be_r_mte',
'helper_sve_ld1hss_be_r_mte',
'helper_sve_ld1hds_be_r_mte',
'helper_sve_ld1sdu_le_r_mte',
'helper_sve_ld1sds_le_r_mte',
'helper_sve_ld1sdu_be_r_mte',
'helper_sve_ld1sds_be_r_mte',
'helper_sve_ldsds_be_zd',
'helper_sve_ldsds_le_zd',
'helper_sve_ldsds_be_zss',

1
qemu/target/arm/cpu.h
View file

@ -3263,6 +3263,7 @@ static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x)
* generic target bits directly.
*/
#define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0)
#define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1)
/*
* Naming convention for isar_feature functions:

58
qemu/target/arm/helper-sve.h
View file

@ -1196,6 +1196,64 @@ DEF_HELPER_FLAGS_4(sve_ld1sds_le_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld1sdu_be_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld1sds_be_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld1bb_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld2bb_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld3bb_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld4bb_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld1hh_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld2hh_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld3hh_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld4hh_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld1hh_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld2hh_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld3hh_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld4hh_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld1ss_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld2ss_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld3ss_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld4ss_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld1ss_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld2ss_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld3ss_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld4ss_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld1dd_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld2dd_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld3dd_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld4dd_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld1dd_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld2dd_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld3dd_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld4dd_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld1bhu_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld1bsu_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld1bdu_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld1bhs_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld1bss_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld1bds_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld1hsu_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld1hdu_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld1hss_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld1hds_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld1hsu_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld1hdu_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld1hss_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld1hds_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld1sdu_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld1sds_le_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld1sdu_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld1sds_be_r_mte, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ldff1bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ldff1bhu_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ldff1bsu_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32)

6
qemu/target/arm/internals.h
View file

@ -1310,6 +1310,12 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
#define LOG2_TAG_GRANULE 4
#define TAG_GRANULE (1 << LOG2_TAG_GRANULE)
/*
* The SVE simd_data field, for memory ops, contains either
* rd (5 bits) or a shift count (2 bits).
*/
#define SVE_MTEDESC_SHIFT 5
/* Bits within a descriptor passed to the helper_mte_check* functions. */
FIELD(MTEDESC, MIDX, 0, 4)
FIELD(MTEDESC, TBI, 4, 2)

217
qemu/target/arm/sve_helper.c
View file

@ -4393,15 +4393,88 @@ static void sve_cont_ldst_watchpoints(SVEContLdSt *info, CPUARMState *env,
#endif
}
typedef uint64_t mte_check_fn(CPUARMState *, uint32_t, uint64_t, uintptr_t);
static inline
void sve_cont_ldst_mte_check_int(SVEContLdSt *info, CPUARMState *env,
uint64_t *vg, target_ulong addr, int esize,
int msize, uint32_t mtedesc, uintptr_t ra,
mte_check_fn *check)
{
intptr_t mem_off, reg_off, reg_last;
/* Process the page only if MemAttr == Tagged. */
if (arm_tlb_mte_tagged(&info->page[0].attrs)) {
mem_off = info->mem_off_first[0];
reg_off = info->reg_off_first[0];
reg_last = info->reg_off_split;
if (reg_last < 0) {
reg_last = info->reg_off_last[0];
}
do {
uint64_t pg = vg[reg_off >> 6];
do {
if ((pg >> (reg_off & 63)) & 1) {
check(env, mtedesc, addr, ra);
}
reg_off += esize;
mem_off += msize;
} while (reg_off <= reg_last && (reg_off & 63));
} while (reg_off <= reg_last);
}
mem_off = info->mem_off_first[1];
if (mem_off >= 0 && arm_tlb_mte_tagged(&info->page[1].attrs)) {
reg_off = info->reg_off_first[1];
reg_last = info->reg_off_last[1];
do {
uint64_t pg = vg[reg_off >> 6];
do {
if ((pg >> (reg_off & 63)) & 1) {
check(env, mtedesc, addr, ra);
}
reg_off += esize;
mem_off += msize;
} while (reg_off & 63);
} while (reg_off <= reg_last);
}
}
typedef void sve_cont_ldst_mte_check_fn(SVEContLdSt *info, CPUARMState *env,
uint64_t *vg, target_ulong addr,
int esize, int msize, uint32_t mtedesc,
uintptr_t ra);
static void sve_cont_ldst_mte_check1(SVEContLdSt *info, CPUARMState *env,
uint64_t *vg, target_ulong addr,
int esize, int msize, uint32_t mtedesc,
uintptr_t ra)
{
sve_cont_ldst_mte_check_int(info, env, vg, addr, esize, msize,
mtedesc, ra, mte_check1_);
}
static void sve_cont_ldst_mte_checkN(SVEContLdSt *info, CPUARMState *env,
uint64_t *vg, target_ulong addr,
int esize, int msize, uint32_t mtedesc,
uintptr_t ra)
{
sve_cont_ldst_mte_check_int(info, env, vg, addr, esize, msize,
mtedesc, ra, mte_checkN_);
}
/*
* Common helper for all contiguous 1,2,3,4-register predicated stores.
*/
static inline
void sve_ldN_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
uint32_t desc, const uintptr_t retaddr,
const int esz, const int msz, const int N,
const int esz, const int msz, const int N, uint32_t mtedesc,
sve_ldst1_host_fn *host_fn,
sve_ldst1_tlb_fn *tlb_fn)
sve_ldst1_tlb_fn *tlb_fn,
sve_cont_ldst_mte_check_fn *mte_check_fn)
{
const unsigned rd = simd_data(desc);
const intptr_t reg_max = simd_oprsz(desc);
@ -4426,7 +4499,14 @@ void sve_ldN_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
sve_cont_ldst_watchpoints(&info, env, vg, addr, 1 << esz, N << msz,
BP_MEM_READ, retaddr);
/* TODO: MTE check. */
/*
* Handle mte checks for all active elements.
* Since TBI must be set for MTE, !mtedesc => !mte_active.
*/
if (mte_check_fn && mtedesc) {
mte_check_fn(&info, env, vg, addr, 1 << esz, N << msz,
mtedesc, retaddr);
}
flags = info.page[0].flags | info.page[1].flags;
if (unlikely(flags != 0)) {
@ -4532,26 +4612,67 @@ void sve_ldN_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
}
}
#define DO_LD1_1(NAME, ESZ) \
void HELPER(sve_##NAME##_r)(CPUARMState *env, void *vg, \
target_ulong addr, uint32_t desc) \
{ \
sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, 1, \
sve_##NAME##_host, sve_##NAME##_tlb); \
static inline
void sve_ldN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr,
uint32_t desc, const uintptr_t ra,
const int esz, const int msz, const int N,
sve_ldst1_host_fn *host_fn,
sve_ldst1_tlb_fn *tlb_fn)
{
uint32_t mtedesc = desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
int bit55 = extract64(addr, 55, 1);
/* Remove mtedesc from the normal sve descriptor. */
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
/* Perform gross MTE suppression early. */
if (!tbi_check(desc, bit55) ||
tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
mtedesc = 0;
}
sve_ldN_r(env, vg, addr, desc, ra, esz, msz, N, mtedesc, host_fn, tlb_fn,
N == 1 ? sve_cont_ldst_mte_check1 : sve_cont_ldst_mte_checkN);
}
#define DO_LD1_2(NAME, ESZ, MSZ) \
void HELPER(sve_##NAME##_le_r)(CPUARMState *env, void *vg, \
target_ulong addr, uint32_t desc) \
{ \
sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, \
sve_##NAME##_le_host, sve_##NAME##_le_tlb); \
} \
void HELPER(sve_##NAME##_be_r)(CPUARMState *env, void *vg, \
target_ulong addr, uint32_t desc) \
{ \
sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, \
sve_##NAME##_be_host, sve_##NAME##_be_tlb); \
#define DO_LD1_1(NAME, ESZ) \
void HELPER(sve_##NAME##_r)(CPUARMState *env, void *vg, \
target_ulong addr, uint32_t desc) \
{ \
sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, 1, 0, \
sve_##NAME##_host, sve_##NAME##_tlb, NULL); \
} \
void HELPER(sve_##NAME##_r_mte)(CPUARMState *env, void *vg, \
target_ulong addr, uint32_t desc) \
{ \
sve_ldN_r_mte(env, vg, addr, desc, GETPC(), ESZ, MO_8, 1, \
sve_##NAME##_host, sve_##NAME##_tlb); \
}
#define DO_LD1_2(NAME, ESZ, MSZ) \
void HELPER(sve_##NAME##_le_r)(CPUARMState *env, void *vg, \
target_ulong addr, uint32_t desc) \
{ \
sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, 0, \
sve_##NAME##_le_host, sve_##NAME##_le_tlb, NULL); \
} \
void HELPER(sve_##NAME##_be_r)(CPUARMState *env, void *vg, \
target_ulong addr, uint32_t desc) \
{ \
sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, 0, \
sve_##NAME##_be_host, sve_##NAME##_be_tlb, NULL); \
} \
void HELPER(sve_##NAME##_le_r_mte)(CPUARMState *env, void *vg, \
target_ulong addr, uint32_t desc) \
{ \
sve_ldN_r_mte(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, \
sve_##NAME##_le_host, sve_##NAME##_le_tlb); \
} \
void HELPER(sve_##NAME##_be_r_mte)(CPUARMState *env, void *vg, \
target_ulong addr, uint32_t desc) \
{ \
sve_ldN_r_mte(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, \
sve_##NAME##_be_host, sve_##NAME##_be_tlb); \
}
DO_LD1_1(ld1bb, MO_8)
@ -4577,26 +4698,44 @@ DO_LD1_2(ld1dd, MO_64, MO_64)
#undef DO_LD1_1
#undef DO_LD1_2
#define DO_LDN_1(N) \
void HELPER(sve_ld##N##bb_r)(CPUARMState *env, void *vg, \
target_ulong addr, uint32_t desc) \
{ \
sve_ldN_r(env, vg, addr, desc, GETPC(), MO_8, MO_8, N, \
sve_ld1bb_host, sve_ld1bb_tlb); \
#define DO_LDN_1(N) \
void HELPER(sve_ld##N##bb_r)(CPUARMState *env, void *vg, \
target_ulong addr, uint32_t desc) \
{ \
sve_ldN_r(env, vg, addr, desc, GETPC(), MO_8, MO_8, N, 0, \
sve_ld1bb_host, sve_ld1bb_tlb, NULL); \
} \
void HELPER(sve_ld##N##bb_r_mte)(CPUARMState *env, void *vg, \
target_ulong addr, uint32_t desc) \
{ \
sve_ldN_r_mte(env, vg, addr, desc, GETPC(), MO_8, MO_8, N, \
sve_ld1bb_host, sve_ld1bb_tlb); \
}
#define DO_LDN_2(N, SUFF, ESZ) \
void HELPER(sve_ld##N##SUFF##_le_r)(CPUARMState *env, void *vg, \
target_ulong addr, uint32_t desc) \
{ \
sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, \
sve_ld1##SUFF##_le_host, sve_ld1##SUFF##_le_tlb); \
} \
void HELPER(sve_ld##N##SUFF##_be_r)(CPUARMState *env, void *vg, \
target_ulong addr, uint32_t desc) \
{ \
sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, \
sve_ld1##SUFF##_be_host, sve_ld1##SUFF##_be_tlb); \
#define DO_LDN_2(N, SUFF, ESZ) \
void HELPER(sve_ld##N##SUFF##_le_r)(CPUARMState *env, void *vg, \
target_ulong addr, uint32_t desc) \
{ \
sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, 0, \
sve_ld1##SUFF##_le_host, sve_ld1##SUFF##_le_tlb, NULL); \
} \
void HELPER(sve_ld##N##SUFF##_be_r)(CPUARMState *env, void *vg, \
target_ulong addr, uint32_t desc) \
{ \
sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, 0, \
sve_ld1##SUFF##_be_host, sve_ld1##SUFF##_be_tlb, NULL); \
} \
void HELPER(sve_ld##N##SUFF##_le_r_mte)(CPUARMState *env, void *vg, \
target_ulong addr, uint32_t desc) \
{ \
sve_ldN_r_mte(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, \
sve_ld1##SUFF##_le_host, sve_ld1##SUFF##_le_tlb); \
} \
void HELPER(sve_ld##N##SUFF##_be_r_mte)(CPUARMState *env, void *vg, \
target_ulong addr, uint32_t desc) \
{ \
sve_ldN_r_mte(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, \
sve_ld1##SUFF##_be_host, sve_ld1##SUFF##_be_tlb); \
}
DO_LDN_1(2)

186
qemu/target/arm/translate-sve.c
View file

@ -4725,19 +4725,33 @@ static const uint8_t dtype_esz[16] = {
};
static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
int dtype, gen_helper_gvec_mem *fn)
int dtype, uint32_t mte_n, bool is_write,
gen_helper_gvec_mem *fn)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
unsigned vsz = vec_full_reg_size(s);
TCGv_ptr t_pg;
TCGv_i32 t_desc;
int desc;
int desc = 0;
/* For e.g. LD4, there are not enough arguments to pass all 4
/*
* For e.g. LD4, there are not enough arguments to pass all 4
* registers as pointers, so encode the regno into the data field.
* For consistency, do this even for LD1.
* TODO: mte_n check here while callers are updated.
*/
desc = simd_desc(vsz, vsz, zt);
if (mte_n && s->mte_active[0]) {
int msz = dtype_msz(dtype);
desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
desc = FIELD_DP32(desc, MTEDESC, ESIZE, 1 << msz);
desc = FIELD_DP32(desc, MTEDESC, TSIZE, mte_n << msz);
desc <<= SVE_MTEDESC_SHIFT;
}
desc = simd_desc(vsz, vsz, zt | desc);
t_desc = tcg_const_i32(tcg_ctx, desc);
t_pg = tcg_temp_new_ptr(tcg_ctx);
@ -4751,64 +4765,132 @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
static void do_ld_zpa(DisasContext *s, int zt, int pg,
TCGv_i64 addr, int dtype, int nreg)
{
static gen_helper_gvec_mem * const fns[2][16][4] = {
/* Little-endian */
{ { gen_helper_sve_ld1bb_r, gen_helper_sve_ld2bb_r,
static gen_helper_gvec_mem * const fns[2][2][16][4] = {
{ /* mte inactive, little-endian */
{ { gen_helper_sve_ld1bb_r, gen_helper_sve_ld2bb_r,
gen_helper_sve_ld3bb_r, gen_helper_sve_ld4bb_r },
{ gen_helper_sve_ld1bhu_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1bsu_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1bdu_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1bhu_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1bsu_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1bdu_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1sds_le_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1hh_le_r, gen_helper_sve_ld2hh_le_r,
gen_helper_sve_ld3hh_le_r, gen_helper_sve_ld4hh_le_r },
{ gen_helper_sve_ld1hsu_le_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1hdu_le_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1sds_le_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1hh_le_r, gen_helper_sve_ld2hh_le_r,
gen_helper_sve_ld3hh_le_r, gen_helper_sve_ld4hh_le_r },
{ gen_helper_sve_ld1hsu_le_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1hdu_le_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1hds_le_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1hss_le_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1ss_le_r, gen_helper_sve_ld2ss_le_r,
gen_helper_sve_ld3ss_le_r, gen_helper_sve_ld4ss_le_r },
{ gen_helper_sve_ld1sdu_le_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1hds_le_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1hss_le_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1ss_le_r, gen_helper_sve_ld2ss_le_r,
gen_helper_sve_ld3ss_le_r, gen_helper_sve_ld4ss_le_r },
{ gen_helper_sve_ld1sdu_le_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1bds_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1bss_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1bhs_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1dd_le_r, gen_helper_sve_ld2dd_le_r,
gen_helper_sve_ld3dd_le_r, gen_helper_sve_ld4dd_le_r } },
{ gen_helper_sve_ld1bds_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1bss_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1bhs_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1dd_le_r, gen_helper_sve_ld2dd_le_r,
gen_helper_sve_ld3dd_le_r, gen_helper_sve_ld4dd_le_r } },
/* Big-endian */
{ { gen_helper_sve_ld1bb_r, gen_helper_sve_ld2bb_r,
gen_helper_sve_ld3bb_r, gen_helper_sve_ld4bb_r },
{ gen_helper_sve_ld1bhu_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1bsu_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1bdu_r, NULL, NULL, NULL },
/* mte inactive, big-endian */
{ { gen_helper_sve_ld1bb_r, gen_helper_sve_ld2bb_r,
gen_helper_sve_ld3bb_r, gen_helper_sve_ld4bb_r },
{ gen_helper_sve_ld1bhu_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1bsu_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1bdu_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1sds_be_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1hh_be_r, gen_helper_sve_ld2hh_be_r,
gen_helper_sve_ld3hh_be_r, gen_helper_sve_ld4hh_be_r },
{ gen_helper_sve_ld1hsu_be_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1hdu_be_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1sds_be_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1hh_be_r, gen_helper_sve_ld2hh_be_r,
gen_helper_sve_ld3hh_be_r, gen_helper_sve_ld4hh_be_r },
{ gen_helper_sve_ld1hsu_be_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1hdu_be_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1hds_be_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1hss_be_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1ss_be_r, gen_helper_sve_ld2ss_be_r,
gen_helper_sve_ld3ss_be_r, gen_helper_sve_ld4ss_be_r },
{ gen_helper_sve_ld1sdu_be_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1hds_be_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1hss_be_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1ss_be_r, gen_helper_sve_ld2ss_be_r,
gen_helper_sve_ld3ss_be_r, gen_helper_sve_ld4ss_be_r },
{ gen_helper_sve_ld1sdu_be_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1bds_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1bss_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1bhs_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1dd_be_r, gen_helper_sve_ld2dd_be_r,
gen_helper_sve_ld3dd_be_r, gen_helper_sve_ld4dd_be_r } }
{ gen_helper_sve_ld1bds_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1bss_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1bhs_r, NULL, NULL, NULL },
{ gen_helper_sve_ld1dd_be_r, gen_helper_sve_ld2dd_be_r,
gen_helper_sve_ld3dd_be_r, gen_helper_sve_ld4dd_be_r } } },
{ /* mte active, little-endian */
{ { gen_helper_sve_ld1bb_r_mte,
gen_helper_sve_ld2bb_r_mte,
gen_helper_sve_ld3bb_r_mte,
gen_helper_sve_ld4bb_r_mte },
{ gen_helper_sve_ld1bhu_r_mte, NULL, NULL, NULL },
{ gen_helper_sve_ld1bsu_r_mte, NULL, NULL, NULL },
{ gen_helper_sve_ld1bdu_r_mte, NULL, NULL, NULL },
{ gen_helper_sve_ld1sds_le_r_mte, NULL, NULL, NULL },
{ gen_helper_sve_ld1hh_le_r_mte,
gen_helper_sve_ld2hh_le_r_mte,
gen_helper_sve_ld3hh_le_r_mte,
gen_helper_sve_ld4hh_le_r_mte },
{ gen_helper_sve_ld1hsu_le_r_mte, NULL, NULL, NULL },
{ gen_helper_sve_ld1hdu_le_r_mte, NULL, NULL, NULL },
{ gen_helper_sve_ld1hds_le_r_mte, NULL, NULL, NULL },
{ gen_helper_sve_ld1hss_le_r_mte, NULL, NULL, NULL },
{ gen_helper_sve_ld1ss_le_r_mte,
gen_helper_sve_ld2ss_le_r_mte,
gen_helper_sve_ld3ss_le_r_mte,
gen_helper_sve_ld4ss_le_r_mte },
{ gen_helper_sve_ld1sdu_le_r_mte, NULL, NULL, NULL },
{ gen_helper_sve_ld1bds_r_mte, NULL, NULL, NULL },
{ gen_helper_sve_ld1bss_r_mte, NULL, NULL, NULL },
{ gen_helper_sve_ld1bhs_r_mte, NULL, NULL, NULL },
{ gen_helper_sve_ld1dd_le_r_mte,
gen_helper_sve_ld2dd_le_r_mte,
gen_helper_sve_ld3dd_le_r_mte,
gen_helper_sve_ld4dd_le_r_mte } },
/* mte active, big-endian */
{ { gen_helper_sve_ld1bb_r_mte,
gen_helper_sve_ld2bb_r_mte,
gen_helper_sve_ld3bb_r_mte,
gen_helper_sve_ld4bb_r_mte },
{ gen_helper_sve_ld1bhu_r_mte, NULL, NULL, NULL },
{ gen_helper_sve_ld1bsu_r_mte, NULL, NULL, NULL },
{ gen_helper_sve_ld1bdu_r_mte, NULL, NULL, NULL },
{ gen_helper_sve_ld1sds_be_r_mte, NULL, NULL, NULL },
{ gen_helper_sve_ld1hh_be_r_mte,
gen_helper_sve_ld2hh_be_r_mte,
gen_helper_sve_ld3hh_be_r_mte,
gen_helper_sve_ld4hh_be_r_mte },
{ gen_helper_sve_ld1hsu_be_r_mte, NULL, NULL, NULL },
{ gen_helper_sve_ld1hdu_be_r_mte, NULL, NULL, NULL },
{ gen_helper_sve_ld1hds_be_r_mte, NULL, NULL, NULL },
{ gen_helper_sve_ld1hss_be_r_mte, NULL, NULL, NULL },
{ gen_helper_sve_ld1ss_be_r_mte,
gen_helper_sve_ld2ss_be_r_mte,
gen_helper_sve_ld3ss_be_r_mte,
gen_helper_sve_ld4ss_be_r_mte },
{ gen_helper_sve_ld1sdu_be_r_mte, NULL, NULL, NULL },
{ gen_helper_sve_ld1bds_r_mte, NULL, NULL, NULL },
{ gen_helper_sve_ld1bss_r_mte, NULL, NULL, NULL },
{ gen_helper_sve_ld1bhs_r_mte, NULL, NULL, NULL },
{ gen_helper_sve_ld1dd_be_r_mte,
gen_helper_sve_ld2dd_be_r_mte,
gen_helper_sve_ld3dd_be_r_mte,
gen_helper_sve_ld4dd_be_r_mte } } },
};
gen_helper_gvec_mem *fn = fns[s->be_data == MO_BE][dtype][nreg];
gen_helper_gvec_mem *fn
= fns[s->mte_active[0]][s->be_data == MO_BE][dtype][nreg];
/* While there are holes in the table, they are not
/*
* While there are holes in the table, they are not
* accessible via the instruction encoding.
*/
assert(fn != NULL);
do_mem_zpa(s, zt, pg, addr, dtype, fn);
do_mem_zpa(s, zt, pg, addr, dtype, nreg, false, fn);
}
static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a)
@ -4893,7 +4975,7 @@ static bool trans_LDFF1_zprr(DisasContext *s, arg_rprr_load *a)
TCGv_i64 addr = new_tmp_a64(s);
tcg_gen_shli_i64(tcg_ctx, addr, cpu_reg(s, a->rm), dtype_msz(a->dtype));
tcg_gen_add_i64(tcg_ctx, addr, addr, cpu_reg_sp(s, a->rn));
do_mem_zpa(s, a->rd, a->pg, addr, a->dtype,
do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, 0, false,
fns[s->be_data == MO_BE][a->dtype]);
}
return true;
@ -4953,7 +5035,7 @@ static bool trans_LDNF1_zpri(DisasContext *s, arg_rpri_load *a)
TCGv_i64 addr = new_tmp_a64(s);
tcg_gen_addi_i64(tcg_ctx, addr, cpu_reg_sp(s, a->rn), off);
do_mem_zpa(s, a->rd, a->pg, addr, a->dtype,
do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, 0, false,
fns[s->be_data == MO_BE][a->dtype]);
}
return true;
@ -5159,7 +5241,7 @@ static void do_st_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
fn = fn_multiple[be][nreg - 1][msz];
}
assert(fn != NULL);
do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), fn);
do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), 0, true, fn);
}
static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a)