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target-m68k: Use setcond for scc

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Backports commit b459e3eccfae7fe83e30187c391de00bccf4f51d from qemu
This commit is contained in:
Richard Henderson 2018-02-27 10:10:43 -05:00 committed by Lioncash
parent ed6feb9329
commit 672a28173f
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 12 additions and 9 deletions
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21
qemu/target-m68k/translate.c
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@ -862,19 +862,22 @@ static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
DISAS_INSN(scc)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGLabel *l1;
DisasCompare c;
int cond;
TCGv reg;
TCGv reg, tmp;
cond = (insn >> 8) & 0xf;
gen_cc_cond(&c, s, cond);
tmp = tcg_temp_new(tcg_ctx);
tcg_gen_setcond_i32(tcg_ctx, c.tcond, tmp, c.v1, c.v2);
free_cond(s, &c);
l1 = gen_new_label(tcg_ctx);
cond = (insn >> 8) & 0xf;
reg = DREG(insn, 0);
tcg_gen_andi_i32(tcg_ctx, reg, reg, 0xffffff00);
/* This is safe because we modify the reg directly, with no other values
live. */
gen_jmpcc(s, cond ^ 1, l1);
tcg_gen_ori_i32(tcg_ctx, reg, reg, 0xff);
gen_set_label(tcg_ctx, l1);
tcg_gen_neg_i32(tcg_ctx, tmp, tmp);
tcg_gen_deposit_i32(tcg_ctx, reg, reg, tmp, 0, 8);
tcg_temp_free(tcg_ctx, tmp);
}
/* Force a TB lookup after an instruction that changes the CPU state. */