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target-arm: make CSSELR banked

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Rename CSSELR (cache size selection register) and add secure
instance (AArch32).

Backports commit b85a1fd61c4d72c7928cd9b70f9f59fb2895936d from qemu
This commit is contained in:
Fabian Aggeler 2018-02-11 19:34:40 -05:00 committed by Lioncash
parent 44fc779c6a
commit 673cb7d93e
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 19 additions and 3 deletions
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10
qemu/target-arm/cpu.h
View file

@ -179,7 +179,15 @@ typedef struct CPUARMState {
/* System control coprocessor (cp15) */
struct {
uint32_t c0_cpuid;
uint64_t c0_cssel; /* Cache size selection. */
union { /* Cache size selection */
struct {
uint64_t _unused_csselr0;
uint64_t csselr_ns;
uint64_t _unused_csselr1;
uint64_t csselr_s;
};
uint64_t csselr_el[4];
};
union { /* System control register. */
struct {
uint64_t _unused_sctlr;

12
qemu/target-arm/helper.c
View file

@ -660,7 +660,14 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
ARMCPU *cpu = arm_env_get_cpu(env);
return cpu->ccsidr[env->cp15.c0_cssel];
/* Acquire the CSSELR index from the bank corresponding to the CCSIDR
* bank
*/
uint32_t index = A32_BANKED_REG_GET(env, csselr,
ri->secure & ARM_CP_SECSTATE_S);
return cpu->ccsidr[index];
}
static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -755,7 +762,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
ARM_CP_NO_MIGRATE, PL1_R, 0, NULL, 0, 0, {0, 0},
NULL, ccsidr_read, },
{ "CSSELR", 0,0,0, 3,2,0, ARM_CP_STATE_BOTH,
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c0_cssel), {0, 0},
0, PL1_RW, 0, NULL, 0, 0,
{ offsetof(CPUARMState, cp15.csselr_s), offsetof(CPUARMState, cp15.csselr_ns) },
NULL, NULL, csselr_write, },
/* Auxiliary ID register: this actually has an IMPDEF value but for now
* just RAZ for all cores: