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x86: setup FS & GS base

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Backports commit b90427e8d8ac1c98f4817c0bcb5cd2a66c8eaed1 from unicorn.
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naq 2019-08-08 20:21:29 -04:00 committed by Lioncash
parent 4db8802217
commit 6768d02191
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 42 additions and 22 deletions
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2
include/unicorn/x86.h
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@ -89,6 +89,8 @@ typedef enum uc_x86_reg {
UC_X86_REG_FPTAG, UC_X86_REG_FPTAG,
UC_X86_REG_MSR, // Model-Specific Register UC_X86_REG_MSR, // Model-Specific Register
UC_X86_REG_MXCSR, UC_X86_REG_MXCSR,
UC_X86_REG_GS_BASE,
UC_X86_REG_FS_BASE,
UC_X86_REG_ENDING // <-- mark the end of the list of registers UC_X86_REG_ENDING // <-- mark the end of the list of registers
} uc_x86_reg; } uc_x86_reg;

62
qemu/target/i386/unicorn.c
View file

@ -336,6 +336,9 @@ int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
case UC_X86_REG_GS: case UC_X86_REG_GS:
*(int16_t *)value = state->segs[R_GS].selector; *(int16_t *)value = state->segs[R_GS].selector;
continue; continue;
case UC_X86_REG_FS_BASE:
*(uint32_t *)value = (uint32_t)state->segs[R_FS].base;
continue;
} }
// fall-thru // fall-thru
case UC_MODE_32: case UC_MODE_32:
@ -482,7 +485,10 @@ int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
x86_msr_read(uc, (uc_x86_msr *)value); x86_msr_read(uc, (uc_x86_msr *)value);
break; break;
case UC_X86_REG_MXCSR: case UC_X86_REG_MXCSR:
*(uint32_t *)value = X86_CPU(uc, mycpu)->env.mxcsr; *(uint32_t *)value = state->mxcsr;
break;
case UC_X86_REG_FS_BASE:
*(uint32_t *)value = (uint32_t)state->segs[R_FS].base;
break; break;
} }
break; break;
@ -767,7 +773,7 @@ int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
x86_msr_read(uc, (uc_x86_msr *)value); x86_msr_read(uc, (uc_x86_msr *)value);
break; break;
case UC_X86_REG_MXCSR: case UC_X86_REG_MXCSR:
*(uint32_t *)value = X86_CPU(uc, mycpu)->env.mxcsr; *(uint32_t *)value = state->mxcsr;
break; break;
case UC_X86_REG_XMM8: case UC_X86_REG_XMM8:
case UC_X86_REG_XMM9: case UC_X86_REG_XMM9:
@ -779,11 +785,14 @@ int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
case UC_X86_REG_XMM15: case UC_X86_REG_XMM15:
{ {
float64 *dst = (float64*)value; float64 *dst = (float64*)value;
XMMReg *reg = &X86_CPU(uc, mycpu)->env.xmm_regs[regid - UC_X86_REG_XMM0]; ZMMReg *reg = &state->xmm_regs[regid - UC_X86_REG_XMM0];
dst[0] = reg->_d[0]; dst[0] = reg->ZMM_D(0);
dst[1] = reg->_d[1]; dst[1] = reg->ZMM_D(1);
break; break;
} }
case UC_X86_REG_FS_BASE:
*(uint64_t *)value = (uint64_t)state->segs[R_FS].base;
break;
} }
break; break;
#endif #endif
@ -905,6 +914,9 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i
case UC_X86_REG_GS: case UC_X86_REG_GS:
load_seg_16_helper(state, R_GS, *(uint16_t *)value); load_seg_16_helper(state, R_GS, *(uint16_t *)value);
continue; continue;
case UC_X86_REG_FS_BASE:
state->segs[R_FS].base = *(uint32_t *)value;
continue;
} }
// fall-thru // fall-thru
case UC_MODE_32: case UC_MODE_32:
@ -1058,23 +1070,11 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i
x86_msr_write(uc, (uc_x86_msr *)value); x86_msr_write(uc, (uc_x86_msr *)value);
break; break;
case UC_X86_REG_MXCSR: case UC_X86_REG_MXCSR:
cpu_set_mxcsr(&X86_CPU(uc, mycpu)->env, *(uint32_t *)value); cpu_set_mxcsr(state, *(uint32_t *)value);
break; break;
case UC_X86_REG_XMM8: case UC_X86_REG_FS_BASE:
case UC_X86_REG_XMM9: state->segs[R_FS].base = *(uint32_t *)value;
case UC_X86_REG_XMM10: continue;
case UC_X86_REG_XMM11:
case UC_X86_REG_XMM12:
case UC_X86_REG_XMM13:
case UC_X86_REG_XMM14:
case UC_X86_REG_XMM15:
{
float64 *src = (float64*)value;
XMMReg *reg = &X86_CPU(uc, mycpu)->env.xmm_regs[regid - UC_X86_REG_XMM0];
reg->_d[0] = src[0];
reg->_d[1] = src[1];
break;
}
} }
break; break;
@ -1368,8 +1368,26 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i
x86_msr_write(uc, (uc_x86_msr *)value); x86_msr_write(uc, (uc_x86_msr *)value);
break; break;
case UC_X86_REG_MXCSR: case UC_X86_REG_MXCSR:
cpu_set_mxcsr(&X86_CPU(uc, mycpu)->env, *(uint32_t *)value); cpu_set_mxcsr(state, *(uint32_t *)value);
break; break;
case UC_X86_REG_XMM8:
case UC_X86_REG_XMM9:
case UC_X86_REG_XMM10:
case UC_X86_REG_XMM11:
case UC_X86_REG_XMM12:
case UC_X86_REG_XMM13:
case UC_X86_REG_XMM14:
case UC_X86_REG_XMM15:
{
float64 *src = (float64*)value;
ZMMReg *reg = &state->xmm_regs[regid - UC_X86_REG_XMM0];
reg->ZMM_D(0) = src[0];
reg->ZMM_D(1) = src[1];
break;
}
case UC_X86_REG_FS_BASE:
state->segs[R_FS].base = *(uint64_t *)value;
continue;
} }
break; break;
#endif #endif