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target/arm: Convert T16, Reverse bytes
Backports commit ae3002b0218a90f2088817c70b35d3832ec91c18 from qemu
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@ -24,6 +24,7 @@
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&s_rri_rot !extern s rn rd imm rot
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&s_rrrr !extern s rd rn rm ra
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&rrr_rot !extern rd rn rm rot
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&rr !extern rd rm
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&ri !extern rd imm
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&r !extern rm
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&ldst_rr !extern p w u rn rt rm shimm shtype
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@ -195,3 +196,11 @@ SETEND 1011 0110 010 1 E:1 000 &setend
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CPS 1011 0110 011 . 0 A:1 I:1 F:1 &cps mode=0 M=0 %imod
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CPS_v7m 1011 0110 011 im:1 00 I:1 F:1
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}
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# Reverse bytes
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@rdm .... .... .. rm:3 rd:3 &rr
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REV 1011 1010 00 ... ... @rdm
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REV16 1011 1010 01 ... ... @rdm
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REVSH 1011 1010 11 ... ... @rdm
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@ -11083,7 +11083,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
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static void disas_thumb_insn(DisasContext *s, uint32_t insn)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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uint32_t val, op, rm, rn, rd, shift, cond;
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uint32_t val, op, rm, rd, shift, cond;
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int32_t offset;
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int i;
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TCGv_i32 tmp;
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@ -11281,20 +11281,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
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break;
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}
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/* Otherwise this is rev */
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ARCH(6);
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rn = (insn >> 3) & 0x7;
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rd = insn & 0x7;
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tmp = load_reg(s, rn);
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switch (op1) {
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case 0: tcg_gen_bswap32_i32(tcg_ctx, tmp, tmp); break;
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case 1: gen_rev16(s, tmp, tmp); break;
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case 3: gen_revsh(s, tmp, tmp); break;
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default:
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g_assert_not_reached();
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}
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store_reg(s, rd, tmp);
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break;
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/* Otherwise this is rev, in decodetree */
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goto illegal_op;
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}
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case 6: /* setend, cps; in decodetree */
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