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target/arm: [tcg,a64] Port to insn_start

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Incrementally paves the way towards using the generic instruction translation
loop.

Backports commit a68956ad7f8510bdc0b54793c65c62c6a94570a4 from qemu
This commit is contained in:
Lluís Vilanova 2018-03-04 19:27:17 -05:00 committed by Lioncash
parent b9df4e0ca0
commit 67e0d99080
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 46 additions and 23 deletions
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13
qemu/target/arm/translate-a64.c
View file

@ -11506,6 +11506,15 @@ static int aarch64_tr_init_disas_context(DisasContextBase *dcbase,
return max_insns;
}
static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
TCGContext *tcg_ctx = cpu->uc->tcg_ctx;
dc->insn_start_idx = tcg_op_buf_count(tcg_ctx);
tcg_gen_insn_start(tcg_ctx, dc->pc, 0, 0);
}
void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,
TranslationBlock *tb)
{
@ -11559,9 +11568,7 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,
do {
dc->base.num_insns++;
dc->insn_start_idx = tcg_op_buf_count(tcg_ctx);
tcg_gen_insn_start(tcg_ctx, dc->pc, 0, 0);
aarch64_tr_insn_start(&dc->base, cs);
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
CPUBreakpoint *bp;

56
qemu/target/arm/translate.c
View file

@ -12157,6 +12157,34 @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
0);
}
static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
const CPUBreakpoint *bp)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
TCGContext *tcg_ctx = cpu->uc->tcg_ctx;
if (bp->flags & BP_CPU) {
gen_set_condexec(dc);
gen_set_pc_im(dc, dc->pc);
gen_helper_check_breakpoints(tcg_ctx, tcg_ctx->cpu_env);
/* End the TB early; it's likely not going to be executed */
dc->base.is_jmp = DISAS_TOO_MANY;
} else {
gen_exception_internal_insn(dc, 0, EXCP_DEBUG);
/* The address covered by the breakpoint must be
included in [tb->pc, tb->pc + tb->size) in order
to for it to be properly cleared -- thus we
increment the PC here so that the logic setting
tb->size below does the right thing. */
/* TODO: Advance PC by correct instruction length to
* avoid disassembler error messages */
dc->pc += 2;
dc->base.is_jmp = DISAS_NORETURN;
}
return true;
}
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
{
@ -12227,28 +12255,15 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
CPUBreakpoint *bp;
QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
if (bp->pc == dc->pc) {
if (bp->flags & BP_CPU) {
gen_set_condexec(dc);
gen_set_pc_im(dc, dc->pc);
gen_helper_check_breakpoints(tcg_ctx, tcg_ctx->cpu_env);
/* End the TB early; it's likely not going to be executed */
dc->base.is_jmp = DISAS_UPDATE;
} else {
gen_exception_internal_insn(dc, 0, EXCP_DEBUG);
/* The address covered by the breakpoint must be
included in [tb->pc, tb->pc + tb->size) in order
to for it to be properly cleared -- thus we
increment the PC here so that the logic setting
tb->size below does the right thing. */
/* TODO: Advance PC by correct instruction length to
* avoid disassembler error messages */
dc->pc += 2;
goto done_generating;
if (bp->pc == dc->base.pc_next) {
if (arm_tr_breakpoint_check(&dc->base, cs, bp)) {
break;
}
break;
}
}
if (dc->base.is_jmp > DISAS_TOO_MANY) {
break;
}
}
//if (dc->base.num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
@ -12384,6 +12399,7 @@ tb_end:
gen_exception(dc, EXCP_SMC, syn_aa32_smc(), 3);
break;
case DISAS_NEXT:
case DISAS_TOO_MANY:
case DISAS_UPDATE:
gen_set_pc_im(dc, dc->pc);
/* fall through */
@ -12405,6 +12421,7 @@ tb_end:
*/
switch(dc->base.is_jmp) {
case DISAS_NEXT:
case DISAS_TOO_MANY:
gen_goto_tb(dc, 1, dc->pc);
break;
case DISAS_JUMP:
@ -12458,7 +12475,6 @@ tb_end:
}
}
done_generating:
gen_tb_end(tcg_ctx, tb, dc->base.num_insns);
// Unicorn: commented out