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target/arm: Make MPU_RNR register banked for v8M
Make the MPU_RNR register banked if v8M security extensions are enabled. Backports commit 1bc04a8880374407c4b12d82ceb8752e12ff5336 from qemu
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5e14b33c65
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@ -257,7 +257,8 @@ static void arm_cpu_reset(CPUState *s)
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sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
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}
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}
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env->pmsav7.rnr = 0;
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env->pmsav7.rnr[M_REG_NS] = 0;
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env->pmsav7.rnr[M_REG_S] = 0;
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env->pmsav8.mair0[M_REG_NS] = 0;
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env->pmsav8.mair0[M_REG_S] = 0;
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env->pmsav8.mair1[M_REG_NS] = 0;
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@ -538,7 +538,7 @@ typedef struct CPUARMState {
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uint32_t *drbar;
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uint32_t *drsr;
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uint32_t *dracr;
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uint32_t rnr;
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uint32_t rnr[2];
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} pmsav7;
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/* PMSAv8 MPU */
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@ -2147,7 +2147,7 @@ static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
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return 0;
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}
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u32p += env->pmsav7.rnr;
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u32p += env->pmsav7.rnr[M_REG_NS];
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return *u32p;
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}
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@ -2161,7 +2161,7 @@ static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
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return;
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}
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u32p += env->pmsav7.rnr;
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u32p += env->pmsav7.rnr[M_REG_NS];
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tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
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*u32p = value;
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}
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@ -2197,7 +2197,7 @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
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PL1_RW, 0, NULL, 0, offsetof(CPUARMState, pmsav7.dracr), {0, 0},
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NULL, pmsav7_read, pmsav7_write, NULL, NULL, arm_cp_reset_ignore },
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{ "RGNR", 15,6,2, 0,0,0, 0,0,
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PL1_RW, 0, NULL, 0, offsetof(CPUARMState, pmsav7.rnr), {0, 0},
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PL1_RW, 0, NULL, 0, offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]), {0, 0},
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NULL, NULL, pmsav7_rgnr_write, NULL, NULL, arm_cp_reset_ignore },
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REGINFO_SENTINEL
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};
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