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target/arm: Make MPU_RNR register banked for v8M

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Make the MPU_RNR register banked if v8M security extensions are
enabled.

Backports commit 1bc04a8880374407c4b12d82ceb8752e12ff5336 from qemu
This commit is contained in:
Peter Maydell 2018-03-04 21:05:59 -05:00 committed by Lioncash
parent 5e14b33c65
commit 683830d5ac
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 6 additions and 5 deletions
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3
qemu/target/arm/cpu.c
View file

@ -257,7 +257,8 @@ static void arm_cpu_reset(CPUState *s)
sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
} }
} }
env->pmsav7.rnr = 0; env->pmsav7.rnr[M_REG_NS] = 0;
env->pmsav7.rnr[M_REG_S] = 0;
env->pmsav8.mair0[M_REG_NS] = 0; env->pmsav8.mair0[M_REG_NS] = 0;
env->pmsav8.mair0[M_REG_S] = 0; env->pmsav8.mair0[M_REG_S] = 0;
env->pmsav8.mair1[M_REG_NS] = 0; env->pmsav8.mair1[M_REG_NS] = 0;

2
qemu/target/arm/cpu.h
View file

@ -538,7 +538,7 @@ typedef struct CPUARMState {
uint32_t *drbar; uint32_t *drbar;
uint32_t *drsr; uint32_t *drsr;
uint32_t *dracr; uint32_t *dracr;
uint32_t rnr; uint32_t rnr[2];
} pmsav7; } pmsav7;
/* PMSAv8 MPU */ /* PMSAv8 MPU */

6
qemu/target/arm/helper.c
View file

@ -2147,7 +2147,7 @@ static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
return 0; return 0;
} }
u32p += env->pmsav7.rnr; u32p += env->pmsav7.rnr[M_REG_NS];
return *u32p; return *u32p;
} }
@ -2161,7 +2161,7 @@ static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
return; return;
} }
u32p += env->pmsav7.rnr; u32p += env->pmsav7.rnr[M_REG_NS];
tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
*u32p = value; *u32p = value;
} }
@ -2197,7 +2197,7 @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
PL1_RW, 0, NULL, 0, offsetof(CPUARMState, pmsav7.dracr), {0, 0}, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, pmsav7.dracr), {0, 0},
NULL, pmsav7_read, pmsav7_write, NULL, NULL, arm_cp_reset_ignore }, NULL, pmsav7_read, pmsav7_write, NULL, NULL, arm_cp_reset_ignore },
{ "RGNR", 15,6,2, 0,0,0, 0,0, { "RGNR", 15,6,2, 0,0,0, 0,0,
PL1_RW, 0, NULL, 0, offsetof(CPUARMState, pmsav7.rnr), {0, 0}, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]), {0, 0},
NULL, NULL, pmsav7_rgnr_write, NULL, NULL, arm_cp_reset_ignore }, NULL, NULL, pmsav7_rgnr_write, NULL, NULL, arm_cp_reset_ignore },
REGINFO_SENTINEL REGINFO_SENTINEL
}; };