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x86/cpu: Enable MOVDIRI cpu feature

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MOVDIRI moves doubleword or quadword from register to memory through
direct store which is implemented by using write combining (WC) for
writing data directly into memory without caching the data.

The bit definition:
CPUID.(EAX=7,ECX=0):ECX[bit 27] MOVDIRI

The release document ref below link:
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf

Backports commit 24261de4916596d8ab5f5fee67e9e7a19e8325a5 from qemu
This commit is contained in:
Liu Jingqi 2018-12-18 03:46:33 -05:00 committed by Lioncash
parent 94c8893678
commit 6aa3cd24fd
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 2 additions and 1 deletions
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2
qemu/target/i386/cpu.c
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@ -863,7 +863,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
"la57", NULL, NULL, NULL,
NULL, NULL, "rdpid", NULL,
NULL, "cldemote", NULL, NULL,
NULL, "cldemote", NULL, "movdiri",
NULL, NULL, NULL, NULL,
},
.cpuid = {

1
qemu/target/i386/cpu.h
View file

@ -665,6 +665,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_ECX_LA57 (1U << 16)
#define CPUID_7_0_ECX_RDPID (1U << 22)
#define CPUID_7_0_ECX_CLDEMOTE (1U << 25) /* CLDEMOTE Instruction */
#define CPUID_7_0_ECX_MOVDIRI (1U << 27) /* MOVDIRI Instruction */
#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */