yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2024-12-23 18:15:30 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/arm: Rename cp15.c6_rgnr to pmsav7.rnr

Browse source 
Almost all of the PMSAv7 state is in the pmsav7 substruct of
the ARM CPU state structure. The exception is the region
number register, which is in cp15.c6_rgnr. This exception
is a bit odd for M profile, which otherwise generally does
not store state in the cp15 substruct.

Rename cp15.c6_rgnr to pmsav7.rnr accordingly.

Backports commit 8531eb4f614a60e6582d4832b15eee09f7d27874 from qemu
This commit is contained in:
Peter Maydell 2018-03-04 01:18:51 -05:00 committed by Lioncash
parent 266885f50f
commit 6add2f0f65
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 4 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
qemu/target/arm/cpu.h
View file

@ -311,8 +311,6 @@ typedef struct CPUARMState {
uint64_t par_el[4];
};
uint32_t c6_rgnr;
uint32_t c9_insn; /* Cache lockdown registers. */
uint32_t c9_data;
uint64_t c9_pmcr; /* performance monitor control register */
@ -526,6 +524,7 @@ typedef struct CPUARMState {
uint32_t *drbar;
uint32_t *drsr;
uint32_t *dracr;
uint32_t rnr;
} pmsav7;
void *nvic;

6
qemu/target/arm/helper.c
View file

@ -2147,7 +2147,7 @@ static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
return 0;
}
u32p += env->cp15.c6_rgnr;
u32p += env->pmsav7.rnr;
return *u32p;
}
@ -2161,7 +2161,7 @@ static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
return;
}
u32p += env->cp15.c6_rgnr;
u32p += env->pmsav7.rnr;
tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
*u32p = value;
}
@ -2205,7 +2205,7 @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
PL1_RW, 0, NULL, 0, offsetof(CPUARMState, pmsav7.dracr), {0, 0},
NULL, pmsav7_read, pmsav7_write, NULL, NULL, pmsav7_reset },
{ "RGNR", 15,6,2, 0,0,0, 0,0,
PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c6_rgnr), {0, 0},
PL1_RW, 0, NULL, 0, offsetof(CPUARMState, pmsav7.rnr), {0, 0},
NULL, NULL, pmsav7_rgnr_write },
REGINFO_SENTINEL
};