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target-arm: Add the AArch64 view of the Secure physical timer

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On CPUs with EL3, there are two physical timers, one for Secure and one
for Non-secure. Implement this extra timer and the AArch64 registers
which access it.

Backports commit b4d3978c2fdf944e428a46d2850dbd950b6fbe78 from qemu
This commit is contained in:
Peter Maydell 2018-02-14 20:42:45 -05:00 committed by Lioncash
parent 7a482198b2
commit 6c24603b23
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
18 changed files with 93 additions and 1 deletions
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1
qemu/aarch64.h
View file

@ -151,6 +151,7 @@
#define arm_gt_ptimer_cb arm_gt_ptimer_cb_aarch64
#define arm_gt_vtimer_cb arm_gt_vtimer_cb_aarch64
#define arm_gt_htimer_cb arm_gt_htimer_cb_aarch64
#define arm_gt_stimer_cb arm_gt_stimer_cb_aarch64
#define arm_handle_psci_call arm_handle_psci_call_aarch64
#define arm_is_psci_call arm_is_psci_call_aarch64
#define arm_is_secure arm_is_secure_aarch64

1
qemu/aarch64eb.h
View file

@ -151,6 +151,7 @@
#define arm_gt_ptimer_cb arm_gt_ptimer_cb_aarch64eb
#define arm_gt_vtimer_cb arm_gt_vtimer_cb_aarch64eb
#define arm_gt_htimer_cb arm_gt_htimer_cb_aarch64eb
#define arm_gt_stimer_cb arm_gt_stimer_cb_aarch64eb
#define arm_handle_psci_call arm_handle_psci_call_aarch64eb
#define arm_is_psci_call arm_is_psci_call_aarch64eb
#define arm_is_secure arm_is_secure_aarch64eb

1
qemu/arm.h
View file

@ -151,6 +151,7 @@
#define arm_gt_ptimer_cb arm_gt_ptimer_cb_arm
#define arm_gt_vtimer_cb arm_gt_vtimer_cb_arm
#define arm_gt_htimer_cb arm_gt_htimer_cb_arm
#define arm_gt_stimer_cb arm_gt_stimer_cb_arm
#define arm_handle_psci_call arm_handle_psci_call_arm
#define arm_is_psci_call arm_is_psci_call_arm
#define arm_is_secure arm_is_secure_arm

1
qemu/armeb.h
View file

@ -151,6 +151,7 @@
#define arm_gt_ptimer_cb arm_gt_ptimer_cb_armeb
#define arm_gt_vtimer_cb arm_gt_vtimer_cb_armeb
#define arm_gt_htimer_cb arm_gt_htimer_cb_armeb
#define arm_gt_stimer_cb arm_gt_stimer_cb_armeb
#define arm_handle_psci_call arm_handle_psci_call_armeb
#define arm_is_psci_call arm_is_psci_call_armeb
#define arm_is_secure arm_is_secure_armeb

1
qemu/header_gen.py
View file

@ -157,6 +157,7 @@ symbols = (
'arm_gt_ptimer_cb',
'arm_gt_vtimer_cb',
'arm_gt_htimer_cb',
'arm_gt_stimer_cb',
'arm_handle_psci_call',
'arm_is_psci_call',
'arm_is_secure',

1
qemu/m68k.h
View file

@ -151,6 +151,7 @@
#define arm_gt_ptimer_cb arm_gt_ptimer_cb_m68k
#define arm_gt_vtimer_cb arm_gt_vtimer_cb_m68k
#define arm_gt_htimer_cb arm_gt_htimer_cb_m68k
#define arm_gt_stimer_cb arm_gt_stimer_cb_m68k
#define arm_handle_psci_call arm_handle_psci_call_m68k
#define arm_is_psci_call arm_is_psci_call_m68k
#define arm_is_secure arm_is_secure_m68k

1
qemu/mips.h
View file

@ -151,6 +151,7 @@
#define arm_gt_ptimer_cb arm_gt_ptimer_cb_mips
#define arm_gt_vtimer_cb arm_gt_vtimer_cb_mips
#define arm_gt_htimer_cb arm_gt_htimer_cb_mips
#define arm_gt_stimer_cb arm_gt_stimer_cb_mips
#define arm_handle_psci_call arm_handle_psci_call_mips
#define arm_is_psci_call arm_is_psci_call_mips
#define arm_is_secure arm_is_secure_mips

1
qemu/mips64.h
View file

@ -151,6 +151,7 @@
#define arm_gt_ptimer_cb arm_gt_ptimer_cb_mips64
#define arm_gt_vtimer_cb arm_gt_vtimer_cb_mips64
#define arm_gt_htimer_cb arm_gt_htimer_cb_mips64
#define arm_gt_stimer_cb arm_gt_stimer_cb_mips64
#define arm_handle_psci_call arm_handle_psci_call_mips64
#define arm_is_psci_call arm_is_psci_call_mips64
#define arm_is_secure arm_is_secure_mips64

1
qemu/mips64el.h
View file

@ -151,6 +151,7 @@
#define arm_gt_ptimer_cb arm_gt_ptimer_cb_mips64el
#define arm_gt_vtimer_cb arm_gt_vtimer_cb_mips64el
#define arm_gt_htimer_cb arm_gt_htimer_cb_mips64el
#define arm_gt_stimer_cb arm_gt_stimer_cb_mips64el
#define arm_handle_psci_call arm_handle_psci_call_mips64el
#define arm_is_psci_call arm_is_psci_call_mips64el
#define arm_is_secure arm_is_secure_mips64el

1
qemu/mipsel.h
View file

@ -151,6 +151,7 @@
#define arm_gt_ptimer_cb arm_gt_ptimer_cb_mipsel
#define arm_gt_vtimer_cb arm_gt_vtimer_cb_mipsel
#define arm_gt_htimer_cb arm_gt_htimer_cb_mipsel
#define arm_gt_stimer_cb arm_gt_stimer_cb_mipsel
#define arm_handle_psci_call arm_handle_psci_call_mipsel
#define arm_is_psci_call arm_is_psci_call_mipsel
#define arm_is_secure arm_is_secure_mipsel

1
qemu/powerpc.h
View file

@ -151,6 +151,7 @@
#define arm_gt_ptimer_cb arm_gt_ptimer_cb_powerpc
#define arm_gt_vtimer_cb arm_gt_vtimer_cb_powerpc
#define arm_gt_htimer_cb arm_gt_htimer_cb_powerpc
#define arm_gt_stimer_cb arm_gt_stimer_cb_powerpc
#define arm_handle_psci_call arm_handle_psci_call_powerpc
#define arm_is_psci_call arm_is_psci_call_powerpc
#define arm_is_secure arm_is_secure_powerpc

1
qemu/sparc.h
View file

@ -151,6 +151,7 @@
#define arm_gt_ptimer_cb arm_gt_ptimer_cb_sparc
#define arm_gt_vtimer_cb arm_gt_vtimer_cb_sparc
#define arm_gt_htimer_cb arm_gt_htimer_cb_sparc
#define arm_gt_stimer_cb arm_gt_stimer_cb_sparc
#define arm_handle_psci_call arm_handle_psci_call_sparc
#define arm_is_psci_call arm_is_psci_call_sparc
#define arm_is_secure arm_is_secure_sparc

1
qemu/sparc64.h
View file

@ -151,6 +151,7 @@
#define arm_gt_ptimer_cb arm_gt_ptimer_cb_sparc64
#define arm_gt_vtimer_cb arm_gt_vtimer_cb_sparc64
#define arm_gt_htimer_cb arm_gt_htimer_cb_sparc64
#define arm_gt_stimer_cb arm_gt_stimer_cb_sparc64
#define arm_handle_psci_call arm_handle_psci_call_sparc64
#define arm_is_psci_call arm_is_psci_call_sparc64
#define arm_is_secure arm_is_secure_sparc64

1
qemu/target-arm/cpu-qom.h
View file

@ -221,6 +221,7 @@ int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void arm_gt_ptimer_cb(void *opaque);
void arm_gt_vtimer_cb(void *opaque);
void arm_gt_htimer_cb(void *opaque);
void arm_gt_stimer_cb(void *opaque);
#ifdef TARGET_AARCH64
int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);

2
qemu/target-arm/cpu.c
View file

@ -379,6 +379,8 @@ static void arm_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
arm_gt_vtimer_cb, cpu);
cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
arm_gt_htimer_cb, cpu);
cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
arm_gt_stimer_cb, cpu);
//qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
// ARRAY_SIZE(cpu->gt_timer_outputs));
#endif

3
qemu/target-arm/cpu.h
View file

@ -118,7 +118,8 @@ typedef struct ARMGenericTimer {
#define GTIMER_PHYS 0
#define GTIMER_VIRT 1
#define GTIMER_HYP 2
#define NUM_GTIMERS 3
#define GTIMER_SEC 3
#define NUM_GTIMERS 4
typedef struct {
uint64_t raw_tcr;

74
qemu/target-arm/helper.c
View file

@ -1061,6 +1061,32 @@ static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
return gt_timer_access(env, GTIMER_VIRT);
}
static CPAccessResult gt_stimer_access(CPUARMState *env,
const ARMCPRegInfo *ri)
{
/* The AArch64 register view of the secure physical timer is
* always accessible from EL3, and configurably accessible from
* Secure EL1.
*/
switch (arm_current_el(env)) {
case 1:
if (!arm_is_secure(env)) {
return CP_ACCESS_TRAP;
}
if (!(env->cp15.scr_el3 & SCR_ST)) {
return CP_ACCESS_TRAP_EL3;
}
return CP_ACCESS_OK;
case 0:
case 2:
return CP_ACCESS_TRAP;
case 3:
return CP_ACCESS_OK;
default:
g_assert_not_reached();
}
}
static uint64_t gt_get_countervalue(CPUARMState *env)
{
return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
@ -1264,6 +1290,34 @@ static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
gt_ctl_write(env, ri, GTIMER_HYP, value);
}
static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{
gt_timer_reset(env, ri, GTIMER_SEC);
}
static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
gt_cval_write(env, ri, GTIMER_SEC, value);
}
static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
return gt_tval_read(env, ri, GTIMER_SEC);
}
static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
gt_tval_write(env, ri, GTIMER_SEC, value);
}
static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
gt_ctl_write(env, ri, GTIMER_SEC, value);
}
void arm_gt_ptimer_cb(void *opaque)
{
ARMCPU *cpu = opaque;
@ -1285,6 +1339,13 @@ void arm_gt_htimer_cb(void *opaque)
gt_recalc_timer(cpu, GTIMER_HYP);
}
void arm_gt_stimer_cb(void *opaque)
{
ARMCPU *cpu = opaque;
gt_recalc_timer(cpu, GTIMER_SEC);
}
static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
/* Note that CNTFRQ is purely reads-as-written for the benefit
* of software; writing it doesn't actually change the timer frequency.
@ -1351,6 +1412,19 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
{ "CNTV_CVAL_EL0", 0,14,3, 3,3,2, ARM_CP_STATE_AA64,
ARM_CP_IO, PL1_RW | PL0_R, 0, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), {0, 0},
gt_vtimer_access, NULL, gt_virt_cval_write, NULL, raw_write, },
/* Secure timer -- this is actually restricted to only EL3
* and configurably Secure-EL1 via the accessfn.
*/
{ "CNTPS_TVAL_EL1", 0,14,2, 3,7,0, ARM_CP_STATE_AA64, ARM_CP_NO_RAW | ARM_CP_IO,
PL1_RW, 0, NULL, 0, 0, {0, 0},
gt_stimer_access, gt_sec_tval_read, gt_sec_tval_write,
NULL, NULL, gt_sec_timer_reset },
{ "CNTPS_CTL_EL1", 0,14,2, 3,7,1, ARM_CP_STATE_AA64, ARM_CP_IO,
PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl), {0, 0},
gt_stimer_access, NULL, gt_sec_ctl_write, NULL, raw_write },
{ "CNTPS_CVAL_EL1", 0,14,2, 3,7,2, ARM_CP_STATE_AA64, ARM_CP_IO,
PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), {0, 0},
gt_stimer_access, NULL, gt_sec_cval_write, NULL, raw_write },
REGINFO_SENTINEL
};

1
qemu/x86_64.h
View file

@ -151,6 +151,7 @@
#define arm_gt_ptimer_cb arm_gt_ptimer_cb_x86_64
#define arm_gt_vtimer_cb arm_gt_vtimer_cb_x86_64
#define arm_gt_htimer_cb arm_gt_htimer_cb_x86_64
#define arm_gt_stimer_cb arm_gt_stimer_cb_x86_64
#define arm_handle_psci_call arm_handle_psci_call_x86_64
#define arm_is_psci_call arm_is_psci_call_x86_64
#define arm_is_secure arm_is_secure_x86_64