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target/riscv: Add the MSTATUS_MPV_ISSET helper macro

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Add a helper macro MSTATUS_MPV_ISSET() which will determine if the
MSTATUS_MPV bit is set for both 32-bit and 64-bit RISC-V.

Backports commit e44b50b5b2e508fdd24915ab0e44ac49685e1de3 from qemu
This commit is contained in:
Alistair Francis 2020-03-22 02:18:00 -04:00 committed by Lioncash
parent 835b025692
commit 6c3338430a
4 changed files with 15 additions and 4 deletions
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11
qemu/target/riscv/cpu_bits.h
View file

@ -363,8 +363,19 @@
#define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */
#define MSTATUS_TW 0x20000000 /* since: priv-1.10 */ #define MSTATUS_TW 0x20000000 /* since: priv-1.10 */
#define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */ #define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */
#if defined(TARGET_RISCV64)
#define MSTATUS_MTL 0x4000000000ULL #define MSTATUS_MTL 0x4000000000ULL
#define MSTATUS_MPV 0x8000000000ULL #define MSTATUS_MPV 0x8000000000ULL
#elif defined(TARGET_RISCV32)
#define MSTATUS_MTL 0x00000040
#define MSTATUS_MPV 0x00000080
#endif
#ifdef TARGET_RISCV32
# define MSTATUS_MPV_ISSET(env) get_field(env->mstatush, MSTATUS_MPV)
#else
# define MSTATUS_MPV_ISSET(env) get_field(env->mstatus, MSTATUS_MPV)
#endif
#define MSTATUS64_UXL 0x0000000300000000ULL #define MSTATUS64_UXL 0x0000000300000000ULL
#define MSTATUS64_SXL 0x0000000C00000000ULL #define MSTATUS64_SXL 0x0000000C00000000ULL

4
qemu/target/riscv/cpu_helper.c
View file

@ -316,7 +316,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
mode = get_field(env->mstatus, MSTATUS_MPP); mode = get_field(env->mstatus, MSTATUS_MPP);
if (riscv_has_ext(env, RVH) && if (riscv_has_ext(env, RVH) &&
get_field(env->mstatus, MSTATUS_MPV)) { MSTATUS_MPV_ISSET(env)) {
use_background = true; use_background = true;
} }
} }
@ -713,7 +713,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
m_mode_two_stage = env->priv == PRV_M && m_mode_two_stage = env->priv == PRV_M &&
access_type != MMU_INST_FETCH && access_type != MMU_INST_FETCH &&
get_field(env->mstatus, MSTATUS_MPRV) && get_field(env->mstatus, MSTATUS_MPRV) &&
get_field(env->mstatus, MSTATUS_MPV); MSTATUS_MPV_ISSET(env);
hs_mode_two_stage = env->priv == PRV_S && hs_mode_two_stage = env->priv == PRV_S &&
!riscv_cpu_virt_enabled(env) && !riscv_cpu_virt_enabled(env) &&

2
qemu/target/riscv/op_helper.c
View file

@ -145,7 +145,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
target_ulong mstatus = env->mstatus; target_ulong mstatus = env->mstatus;
target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP); target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
target_ulong prev_virt = get_field(mstatus, MSTATUS_MPV); target_ulong prev_virt = MSTATUS_MPV_ISSET(env);
mstatus = set_field(mstatus, mstatus = set_field(mstatus,
env->priv_ver >= PRIV_VERSION_1_10_0 ? env->priv_ver >= PRIV_VERSION_1_10_0 ?
MSTATUS_MIE : MSTATUS_UIE << prev_priv, MSTATUS_MIE : MSTATUS_UIE << prev_priv,

2
qemu/target/riscv/translate.c
View file

@ -784,7 +784,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->virt_enabled = riscv_cpu_virt_enabled(env); ctx->virt_enabled = riscv_cpu_virt_enabled(env);
if (env->priv_ver == PRV_M && if (env->priv_ver == PRV_M &&
get_field(env->mstatus, MSTATUS_MPRV) && get_field(env->mstatus, MSTATUS_MPRV) &&
get_field(env->mstatus, MSTATUS_MPV)) { MSTATUS_MPV_ISSET(env)) {
ctx->virt_enabled = true; ctx->virt_enabled = true;
} else if (env->priv == PRV_S && } else if (env->priv == PRV_S &&
!riscv_cpu_virt_enabled(env) && !riscv_cpu_virt_enabled(env) &&