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target/m68k: use insn_pc to generate instruction fault address

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Backports commit 16a14cdf575a2eda4698930d22b75072537754dd from qemu
This commit is contained in:
Laurent Vivier 2018-03-06 07:51:26 -05:00 committed by Lioncash
parent 3a12e69ad6
commit 6d46cb09dc
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 20 additions and 20 deletions
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40
qemu/target/m68k/translate.c
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@ -1551,12 +1551,12 @@ DISAS_INSN(dbcc)
DISAS_INSN(undef_mac)
{
gen_exception(s, s->pc - 2, EXCP_LINEA);
gen_exception(s, s->insn_pc, EXCP_LINEA);
}
DISAS_INSN(undef_fpu)
{
gen_exception(s, s->pc - 2, EXCP_LINEF);
gen_exception(s, s->insn_pc, EXCP_LINEF);
}
DISAS_INSN(undef)
@ -1565,8 +1565,8 @@ DISAS_INSN(undef)
for the 680x0 series, as well as those that are implemented
but actually illegal for CPU32 or pre-68020. */
qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %08x",
insn, s->pc - 2);
gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED);
insn, s->insn_pc);
gen_exception(s, s->insn_pc, EXCP_UNSUPPORTED);
}
DISAS_INSN(mulw)
@ -2658,7 +2658,7 @@ DISAS_INSN(swap)
DISAS_INSN(bkpt)
{
gen_exception(s, s->pc - 2, EXCP_DEBUG);
gen_exception(s, s->insn_pc, EXCP_DEBUG);
}
DISAS_INSN(pea)
@ -2714,7 +2714,7 @@ DISAS_INSN(pulse)
DISAS_INSN(illegal)
{
gen_exception(s, s->pc - 2, EXCP_ILLEGAL);
gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
}
/* ??? This should be atomic. */
@ -2750,7 +2750,7 @@ DISAS_INSN(mull)
if (ext & 0x400) {
if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
gen_exception(s, s->insn_pc, EXCP_UNSUPPORTED);
return;
}
@ -4408,7 +4408,7 @@ DISAS_INSN(move_from_sr)
TCGv sr;
if (IS_USER(s) && !m68k_feature(env, M68K_FEATURE_M68000)) {
gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
return;
}
sr = gen_get_sr(s);
@ -4418,7 +4418,7 @@ DISAS_INSN(move_from_sr)
DISAS_INSN(move_to_sr)
{
if (IS_USER(s)) {
gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
return;
}
gen_set_sr(env, s, insn, 0);
@ -4430,7 +4430,7 @@ DISAS_INSN(move_from_usp)
TCGContext *tcg_ctx = s->uc->tcg_ctx;
if (IS_USER(s)) {
gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
return;
}
@ -4443,7 +4443,7 @@ DISAS_INSN(move_to_usp)
TCGContext *tcg_ctx = s->uc->tcg_ctx;
if (IS_USER(s)) {
gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
return;
}
@ -4462,7 +4462,7 @@ DISAS_INSN(stop)
uint16_t ext;
if (IS_USER(s)) {
gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
return;
}
@ -4476,10 +4476,10 @@ DISAS_INSN(stop)
DISAS_INSN(rte)
{
if (IS_USER(s)) {
gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
return;
}
gen_exception(s, s->pc - 2, EXCP_RTE);
gen_exception(s, s->insn_pc, EXCP_RTE);
}
DISAS_INSN(movec)
@ -4489,7 +4489,7 @@ DISAS_INSN(movec)
TCGv reg;
if (IS_USER(s)) {
gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
return;
}
@ -4507,7 +4507,7 @@ DISAS_INSN(movec)
DISAS_INSN(intouch)
{
if (IS_USER(s)) {
gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
return;
}
/* ICache fetch. Implement as no-op. */
@ -4516,7 +4516,7 @@ DISAS_INSN(intouch)
DISAS_INSN(cpushl)
{
if (IS_USER(s)) {
gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
return;
}
/* Cache push/invalidate. Implement as no-op. */
@ -4524,7 +4524,7 @@ DISAS_INSN(cpushl)
DISAS_INSN(wddata)
{
gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
}
DISAS_INSN(wdebug)
@ -4532,7 +4532,7 @@ DISAS_INSN(wdebug)
M68kCPU *cpu = m68k_env_get_cpu(env);
if (IS_USER(s)) {
gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
return;
}
/* TODO: Implement wdebug. */
@ -4541,7 +4541,7 @@ DISAS_INSN(wdebug)
DISAS_INSN(trap)
{
gen_exception(s, s->pc - 2, EXCP_TRAP0 + (insn & 0xf));
gen_exception(s, s->insn_pc, EXCP_TRAP0 + (insn & 0xf));
}
static void gen_load_fcr(DisasContext *s, TCGv res, int reg)