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target/arm: Split out vae1_tlbmask

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No functional change, but unify code sequences.

Backports commit b7e0730de32d7079a1447ecbb5616d89de77b823 from qemu
This commit is contained in:
Richard Henderson 2020-03-21 13:53:36 -04:00 committed by Lioncash
parent 4f4c385a8e
commit 6d4a7b84b5
1 changed files with 13 additions and 19 deletions
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32
qemu/target/arm/helper.c
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@ -3714,23 +3714,24 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env,
* Page D4-1736 (DDI0487A.b) * Page D4-1736 (DDI0487A.b)
*/ */
static int vae1_tlbmask(CPUARMState *env)
{
if (arm_is_secure_below_el3(env)) {
return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
} else {
return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0;
}
}
static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value) uint64_t value)
{ {
// UNICORN: TODO: issue #642 // UNICORN: TODO: issue #642
#if 0 #if 0
bool sec = arm_is_secure_below_el3(env); int mask = vae1_tlbmask(env);
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
if (sec) { tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
tlb_flush_by_mmuidx_all_cpus_synced(cs,
ARMMMUIdxBit_S1SE1 |
ARMMMUIdxBit_S1SE0);
} else {
tlb_flush_by_mmuidx_all_cpus_synced(cs,
ARMMMUIdxBit_S12NSE1 |
ARMMMUIdxBit_S12NSE0);
}
#endif #endif
} }
@ -3738,21 +3739,14 @@ static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value) uint64_t value)
{ {
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
int mask = vae1_tlbmask(env);
if (tlb_force_broadcast(env)) { if (tlb_force_broadcast(env)) {
tlbi_aa64_vmalle1is_write(env, NULL, value); tlbi_aa64_vmalle1is_write(env, NULL, value);
return; return;
} }
if (arm_is_secure_below_el3(env)) { tlb_flush_by_mmuidx(cs, mask);
tlb_flush_by_mmuidx(cs,
ARMMMUIdxBit_S1SE1 |
ARMMMUIdxBit_S1SE0);
} else {
tlb_flush_by_mmuidx(cs,
ARMMMUIdxBit_S12NSE1 |
ARMMMUIdxBit_S12NSE0);
}
} }
static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,