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target/arm: Split out vae1_tlbmask
No functional change, but unify code sequences. Backports commit b7e0730de32d7079a1447ecbb5616d89de77b823 from qemu
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@ -3714,23 +3714,24 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env,
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* Page D4-1736 (DDI0487A.b)
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*/
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static int vae1_tlbmask(CPUARMState *env)
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{
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if (arm_is_secure_below_el3(env)) {
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return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
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} else {
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return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0;
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}
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}
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static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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// UNICORN: TODO: issue #642
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#if 0
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bool sec = arm_is_secure_below_el3(env);
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int mask = vae1_tlbmask(env);
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CPUState *cs = env_cpu(env);
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if (sec) {
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tlb_flush_by_mmuidx_all_cpus_synced(cs,
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ARMMMUIdxBit_S1SE1 |
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ARMMMUIdxBit_S1SE0);
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} else {
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tlb_flush_by_mmuidx_all_cpus_synced(cs,
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ARMMMUIdxBit_S12NSE1 |
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ARMMMUIdxBit_S12NSE0);
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}
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tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
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#endif
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}
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@ -3738,21 +3739,14 @@ static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = env_cpu(env);
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int mask = vae1_tlbmask(env);
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if (tlb_force_broadcast(env)) {
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tlbi_aa64_vmalle1is_write(env, NULL, value);
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return;
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}
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if (arm_is_secure_below_el3(env)) {
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tlb_flush_by_mmuidx(cs,
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ARMMMUIdxBit_S1SE1 |
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ARMMMUIdxBit_S1SE0);
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} else {
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tlb_flush_by_mmuidx(cs,
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ARMMMUIdxBit_S12NSE1 |
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ARMMMUIdxBit_S12NSE0);
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}
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tlb_flush_by_mmuidx(cs, mask);
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}
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static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
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