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target/mips: Add availability control for DSP R3 ASE

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Add infrastructure for availability control for DSP R3 ASE MIPS
instructions. Only BPOSGE32C currently belongs to DSP R3 ASE, but
this is likely to be changed in near future.

Backports commit 59e781fbf13a2dede15437d055b09d7ea120dcac from qemu
This commit is contained in:
Stefan Markovic 2018-10-23 13:21:16 -04:00 committed by Lioncash
parent 071fe91d6a
commit 6dd29739a9
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
4 changed files with 23 additions and 6 deletions
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1
qemu/target/mips/cpu.h
View file

@ -795,6 +795,7 @@ struct CPUMIPSState {
/* MIPS DSP resources access. */
#define MIPS_HFLAG_DSP 0x080000 /* Enable access to MIPS DSP resources. */
#define MIPS_HFLAG_DSPR2 0x100000 /* Enable access to MIPS DSPR2 resources. */
#define MIPS_HFLAG_DSPR3 0x20000000 /* Enable access to MIPS DSPR3 resources.*/
/* Extra flag about HWREna register. */
#define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
#define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */

11
qemu/target/mips/internal.h
View file

@ -311,8 +311,8 @@ static inline void compute_hflags(CPUMIPSState *env)
env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE |
MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
MIPS_HFLAG_DSPR3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA |
MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
if (env->CP0_Status & (1 << CP0St_ERL)) {
env->hflags |= MIPS_HFLAG_ERL;
}
@ -359,7 +359,12 @@ static inline void compute_hflags(CPUMIPSState *env)
(env->CP0_Config5 & (1 << CP0C5_SBRI))) {
env->hflags |= MIPS_HFLAG_SBRI;
}
if (env->insn_flags & ASE_DSPR2) {
if (env->insn_flags & ASE_DSPR3) {
if (env->CP0_Status & (1 << CP0St_MX)) {
env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
MIPS_HFLAG_DSPR3;
}
} else if (env->insn_flags & ASE_DSPR2) {
/* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
so enable to access DSPR2 resources. */
if (env->CP0_Status & (1 << CP0St_MX)) {

13
qemu/target/mips/translate.c
View file

@ -2415,6 +2415,17 @@ static inline void check_dspr2(DisasContext *ctx)
}
}
static inline void check_dspr3(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSPR3))) {
if (ctx->insn_flags & ASE_DSP) {
generate_exception_end(ctx, EXCP_DSPDIS);
} else {
generate_exception_end(ctx, EXCP_RI);
}
}
}
/* This code generates a "reserved instruction" exception if the
CPU does not support the instruction set corresponding to flags. */
static inline void check_insn(DisasContext *ctx, uint64_t flags)
@ -20778,7 +20789,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_compute_branch_cp1_nm(ctx, OPC_BC1NEZ, rt, s);
break;
case NM_BPOSGE32C:
check_dspr2(ctx);
check_dspr3(ctx);
{
int32_t imm = extract32(ctx->opcode, 1, 13) |
extract32(ctx->opcode, 0, 1) << 13;

4
qemu/target/mips/translate_init.c
View file

@ -409,7 +409,7 @@ const mips_def_t mips_defs[] =
(0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
0,0,
0,
CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
MMU_TYPE_R4000,
},
{
@ -659,7 +659,7 @@ const mips_def_t mips_defs[] =
0,
(1 << CP0PG_IEC) | (1 << CP0PG_XIE) | (1U << CP0PG_RIE),
0,
CPU_NANOMIPS32 | ASE_DSP | ASE_DSPR2 | ASE_MT,
CPU_NANOMIPS32 | ASE_DSP | ASE_DSPR2 | ASE_DSPR3 | ASE_MT,
MMU_TYPE_R4000,
},
#if defined(TARGET_MIPS64)