mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2025-02-02 15:31:00 +00:00
target-mips: refactor {D}LSA, {D}ALIGN, {D}BITSWAP
Refactor those instructions in order to reuse them for microMIPS32 Release 6. Rearrange gen_move_low32(). Backports commit 1f1b4c008e250f870719ed38fbd0bcc14322fc01 from qemu
This commit is contained in:
Yongbok Kim
Lioncash
parent
14abf22311
commit
6e32aa7c3c
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@ -1725,6 +1725,15 @@ static target_long addr_add(DisasContext *ctx, target_long base,
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return sum;
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}
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static inline void gen_move_low32(TCGContext *s, TCGv ret, TCGv_i64 arg)
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{
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#if defined(TARGET_MIPS64)
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tcg_gen_ext32s_tl(s, ret, arg);
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#else
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tcg_gen_trunc_i64_tl(s, ret, arg);
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#endif
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}
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static inline void check_cp0_enabled(DisasContext *ctx)
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{
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if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0)))
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@ -4904,17 +4913,96 @@ static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd)
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tcg_temp_free(tcg_ctx, t0);
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}
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#ifndef CONFIG_USER_ONLY
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/* CP0 (MMU and control) */
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static inline void gen_move_low32(TCGContext *s, TCGv ret, TCGv_i64 arg)
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static void gen_lsa(DisasContext *ctx, int opc, int rd, int rs, int rt,
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int imm2)
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{
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#if defined(TARGET_MIPS64)
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tcg_gen_ext32s_tl(s, ret, arg);
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#else
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tcg_gen_trunc_i64_tl(s, ret, arg);
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#endif
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGv **cpu_gpr = (TCGv **)tcg_ctx->cpu_gpr;
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TCGv t0;
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TCGv t1;
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if (rd == 0) {
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/* Treat as NOP. */
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return;
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}
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t0 = tcg_temp_new(tcg_ctx);
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t1 = tcg_temp_new(tcg_ctx);
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gen_load_gpr(ctx, t0, rs);
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gen_load_gpr(ctx, t1, rt);
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tcg_gen_shli_tl(tcg_ctx, t0, t0, imm2 + 1);
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tcg_gen_add_tl(tcg_ctx, *cpu_gpr[rd], t0, t1);
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if (opc == OPC_LSA) {
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tcg_gen_ext32s_tl(tcg_ctx, *cpu_gpr[rd], *cpu_gpr[rd]);
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}
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tcg_temp_free(tcg_ctx, t1);
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tcg_temp_free(tcg_ctx, t0);
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}
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static void gen_align(DisasContext *ctx, int opc, int rd, int rs, int rt,
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int bp)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGv **cpu_gpr = (TCGv **)tcg_ctx->cpu_gpr;
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TCGv t0;
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if (rd == 0) {
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/* Treat as NOP. */
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return;
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}
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t0 = tcg_temp_new(tcg_ctx);
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gen_load_gpr(ctx, t0, rt);
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if (bp == 0) {
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tcg_gen_mov_tl(tcg_ctx, *cpu_gpr[rd], t0);
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} else {
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TCGv t1 = tcg_temp_new(tcg_ctx);
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gen_load_gpr(ctx, t1, rs);
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switch (opc) {
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case OPC_ALIGN:
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{
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TCGv_i64 t2 = tcg_temp_new_i64(tcg_ctx);
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tcg_gen_concat_tl_i64(tcg_ctx, t2, t1, t0);
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tcg_gen_shri_i64(tcg_ctx, t2, t2, 8 * (4 - bp));
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gen_move_low32(tcg_ctx, *cpu_gpr[rd], t2);
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tcg_temp_free_i64(tcg_ctx, t2);
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}
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break;
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case OPC_DALIGN:
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tcg_gen_shli_tl(tcg_ctx, t0, t0, 8 * bp);
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tcg_gen_shri_tl(tcg_ctx, t1, t1, 8 * (8 - bp));
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tcg_gen_or_tl(tcg_ctx, *cpu_gpr[rd], t1, t0);
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break;
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}
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tcg_temp_free(tcg_ctx, t1);
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}
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tcg_temp_free(tcg_ctx, t0);
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}
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static void gen_bitswap(DisasContext *ctx, int opc, int rd, int rt)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGv **cpu_gpr = (TCGv **)tcg_ctx->cpu_gpr;
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TCGv t0;
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if (rd == 0) {
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/* Treat as NOP. */
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return;
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}
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t0 = tcg_temp_new(tcg_ctx);
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gen_load_gpr(ctx, t0, rt);
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switch (opc) {
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case OPC_BITSWAP:
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gen_helper_bitswap(tcg_ctx, *cpu_gpr[rd], t0);
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break;
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#if defined(TARGET_MIPS64)
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case OPC_DBITSWAP:
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gen_helper_dbitswap(tcg_ctx, *cpu_gpr[rd], t0);
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break;
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#endif
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}
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tcg_temp_free(tcg_ctx, t0);
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}
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#ifndef CONFIG_USER_ONLY
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/* CP0 (MMU and control) */
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static inline void gen_mthc0_entrylo(TCGContext *s, TCGv arg, target_ulong off)
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{
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TCGv_i64 t0 = tcg_temp_new_i64(s);
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@ -16546,7 +16634,6 @@ out:
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static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
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{
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TCGContext *tcg_ctx = env->uc->tcg_ctx;
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TCGv **cpu_gpr = (TCGv **)tcg_ctx->cpu_gpr;
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int rs, rt, rd, sa;
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uint32_t op1, op2;
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@ -16558,18 +16645,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
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op1 = MASK_SPECIAL(ctx->opcode);
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switch (op1) {
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case OPC_LSA:
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if (rd != 0) {
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int imm2 = extract32(ctx->opcode, 6, 3);
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TCGv t0 = tcg_temp_new(tcg_ctx);
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TCGv t1 = tcg_temp_new(tcg_ctx);
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gen_load_gpr(ctx, t0, rs);
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gen_load_gpr(ctx, t1, rt);
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tcg_gen_shli_tl(tcg_ctx, t0, t0, imm2 + 1);
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tcg_gen_add_tl(tcg_ctx, t0, t0, t1);
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tcg_gen_ext32s_tl(tcg_ctx, *cpu_gpr[rd], t0);
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tcg_temp_free(tcg_ctx, t1);
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tcg_temp_free(tcg_ctx, t0);
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}
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gen_lsa(ctx, op1, rd, rs, rt, extract32(ctx->opcode, 6, 2));
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break;
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case OPC_MULT: case OPC_MULTU: case OPC_DIV: case OPC_DIVU:
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op2 = MASK_R6_MULDIV(ctx->opcode);
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@ -16614,17 +16690,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
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#if defined(TARGET_MIPS64)
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case OPC_DLSA:
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check_mips_64(ctx);
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if (rd != 0) {
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int imm2 = extract32(ctx->opcode, 6, 3);
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TCGv t0 = tcg_temp_new(tcg_ctx);
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TCGv t1 = tcg_temp_new(tcg_ctx);
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gen_load_gpr(ctx, t0, rs);
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gen_load_gpr(ctx, t1, rt);
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tcg_gen_shli_tl(tcg_ctx, t0, t0, imm2 + 1);
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tcg_gen_add_tl(tcg_ctx, *cpu_gpr[rd], t0, t1);
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tcg_temp_free(tcg_ctx, t1);
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tcg_temp_free(tcg_ctx, t0);
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}
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gen_lsa(ctx, op1, rd, rs, rt, extract32(ctx->opcode, 6, 2));
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break;
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case R6_OPC_DCLO:
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case R6_OPC_DCLZ:
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@ -17044,40 +17110,20 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
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break;
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case OPC_BSHFL:
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{
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TCGv t0;
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if (rd == 0) {
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/* Treat as NOP. */
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break;
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}
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t0 = tcg_temp_new(tcg_ctx);
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gen_load_gpr(ctx, t0, rt);
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op2 = MASK_BSHFL(ctx->opcode);
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switch (op2) {
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case OPC_ALIGN: case OPC_ALIGN_END:
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sa &= 3;
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if (sa == 0) {
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tcg_gen_mov_tl(tcg_ctx, *cpu_gpr[rd], t0);
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} else {
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TCGv t1 = tcg_temp_new(tcg_ctx);
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TCGv_i64 t2 = tcg_temp_new_i64(tcg_ctx);
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gen_load_gpr(ctx, t1, rs);
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tcg_gen_concat_tl_i64(tcg_ctx, t2, t1, t0);
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tcg_gen_shri_i64(tcg_ctx, t2, t2, 8 * (4 - sa));
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#if defined(TARGET_MIPS64)
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tcg_gen_ext32s_i64(tcg_ctx, *cpu_gpr[rd], t2);
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#else
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tcg_gen_extrl_i64_i32(tcg_ctx, *cpu_gpr[rd], t2);
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#endif
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tcg_temp_free_i64(tcg_ctx, t2);
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tcg_temp_free(tcg_ctx, t1);
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}
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gen_align(ctx, OPC_ALIGN, rd, rs, rt, sa & 3);
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break;
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case OPC_BITSWAP:
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gen_helper_bitswap(tcg_ctx, *cpu_gpr[rd], t0);
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gen_bitswap(ctx, op2, rd, rt);
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break;
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}
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tcg_temp_free(tcg_ctx, t0);
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}
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break;
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#if defined(TARGET_MIPS64)
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@ -17090,34 +17136,20 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
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case OPC_DBSHFL:
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check_mips_64(ctx);
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{
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TCGv t0;
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if (rd == 0) {
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/* Treat as NOP. */
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break;
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}
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t0 = tcg_temp_new(tcg_ctx);
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gen_load_gpr(ctx, t0, rt);
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op2 = MASK_DBSHFL(ctx->opcode);
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switch (op2) {
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case OPC_DALIGN: case OPC_DALIGN_END:
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sa &= 7;
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if (sa == 0) {
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tcg_gen_mov_tl(tcg_ctx, *cpu_gpr[rd], t0);
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} else {
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TCGv t1 = tcg_temp_new(tcg_ctx);
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gen_load_gpr(ctx, t1, rs);
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tcg_gen_shli_tl(tcg_ctx, t0, t0, 8 * sa);
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tcg_gen_shri_tl(tcg_ctx, t1, t1, 8 * (8 - sa));
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tcg_gen_or_tl(tcg_ctx, *cpu_gpr[rd], t1, t0);
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tcg_temp_free(tcg_ctx, t1);
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}
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gen_align(ctx, OPC_DALIGN, rd, rs, rt, sa & 7);
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break;
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case OPC_DBITSWAP:
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gen_helper_dbitswap(tcg_ctx, *cpu_gpr[rd], t0);
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gen_bitswap(ctx, op2, rd, rt);
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break;
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}
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tcg_temp_free(tcg_ctx, t0);
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}
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break;
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#endif
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