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target-mips: microMIPS32 R6 Major instructions

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Add new microMIPS32 Release 6 Major opcode instructions

Backports commit ab39ee452d74855adec91056812b8e1e5166302c from qemu
This commit is contained in:
Yongbok Kim 2018-02-13 22:21:22 -05:00 committed by Lioncash
parent c2550bc28a
commit 6e6ca4dbd4
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 45 additions and 17 deletions
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62
qemu/target-mips/translate.c
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@ -3242,47 +3242,48 @@ static inline void gen_r6_ld(DisasContext *ctx, target_long addr, int reg, int m
tcg_temp_free(tcg_ctx, t0); tcg_temp_free(tcg_ctx, t0);
} }
static inline void gen_pcrel(DisasContext *ctx, int rs, int16_t imm) static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc,
int rs)
{ {
TCGContext *tcg_ctx = ctx->uc->tcg_ctx; TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv **cpu_gpr = (TCGv **)tcg_ctx->cpu_gpr; TCGv **cpu_gpr = (TCGv **)tcg_ctx->cpu_gpr;
target_long offset; target_long offset;
target_long addr; target_long addr;
switch (MASK_OPC_PCREL_TOP2BITS(ctx->opcode)) { switch (MASK_OPC_PCREL_TOP2BITS(opc)) {
case OPC_ADDIUPC: case OPC_ADDIUPC:
if (rs != 0) { if (rs != 0) {
offset = sextract32(ctx->opcode << 2, 0, 21); offset = sextract32(ctx->opcode << 2, 0, 21);
addr = addr_add(ctx, ctx->pc, offset); addr = addr_add(ctx, pc, offset);
tcg_gen_movi_tl(tcg_ctx, *cpu_gpr[rs], addr); tcg_gen_movi_tl(tcg_ctx, *cpu_gpr[rs], addr);
} }
break; break;
case R6_OPC_LWPC: case R6_OPC_LWPC:
offset = sextract32(ctx->opcode << 2, 0, 21); offset = sextract32(ctx->opcode << 2, 0, 21);
addr = addr_add(ctx, ctx->pc, offset); addr = addr_add(ctx, pc, offset);
gen_r6_ld(ctx, addr, rs, ctx->mem_idx, MO_TESL); gen_r6_ld(ctx, addr, rs, ctx->mem_idx, MO_TESL);
break; break;
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case OPC_LWUPC: case OPC_LWUPC:
check_mips_64(ctx); check_mips_64(ctx);
offset = sextract32(ctx->opcode << 2, 0, 21); offset = sextract32(ctx->opcode << 2, 0, 21);
addr = addr_add(ctx, ctx->pc, offset); addr = addr_add(ctx, pc, offset);
gen_r6_ld(ctx, addr, rs, ctx->mem_idx, MO_TEUL); gen_r6_ld(ctx, addr, rs, ctx->mem_idx, MO_TEUL);
break; break;
#endif #endif
default: default:
switch (MASK_OPC_PCREL_TOP5BITS(ctx->opcode)) { switch (MASK_OPC_PCREL_TOP5BITS(opc)) {
case OPC_AUIPC: case OPC_AUIPC:
if (rs != 0) { if (rs != 0) {
offset = imm << 16; offset = sextract32(ctx->opcode, 0, 16) << 16;
addr = addr_add(ctx, ctx->pc, offset); addr = addr_add(ctx, pc, offset);
tcg_gen_movi_tl(tcg_ctx, *cpu_gpr[rs], addr); tcg_gen_movi_tl(tcg_ctx, *cpu_gpr[rs], addr);
} }
break; break;
case OPC_ALUIPC: case OPC_ALUIPC:
if (rs != 0) { if (rs != 0) {
offset = imm << 16; offset = sextract32(ctx->opcode, 0, 16) << 16;
addr = ~0xFFFF & addr_add(ctx, ctx->pc, offset); addr = ~0xFFFF & addr_add(ctx, pc, offset);
tcg_gen_movi_tl(tcg_ctx, *cpu_gpr[rs], addr); tcg_gen_movi_tl(tcg_ctx, *cpu_gpr[rs], addr);
} }
break; break;
@ -3293,7 +3294,7 @@ static inline void gen_pcrel(DisasContext *ctx, int rs, int16_t imm)
case R6_OPC_LDPC + (3 << 16): case R6_OPC_LDPC + (3 << 16):
check_mips_64(ctx); check_mips_64(ctx);
offset = sextract32(ctx->opcode << 3, 0, 21); offset = sextract32(ctx->opcode << 3, 0, 21);
addr = addr_add(ctx, (ctx->pc & ~0x7), offset); addr = addr_add(ctx, (pc & ~0x7), offset);
gen_r6_ld(ctx, addr, rs, ctx->mem_idx, MO_TEQ); gen_r6_ld(ctx, addr, rs, ctx->mem_idx, MO_TEQ);
break; break;
#endif #endif
@ -14928,9 +14929,16 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
break; break;
} }
break; break;
case ADDI32: case ADDI32: /* AUI, LUI */
mips32_op = OPC_ADDI; if (ctx->insn_flags & ISA_MIPS32R6) {
goto do_addi; /* AUI, LUI */
gen_logic_imm(ctx, OPC_LUI, rt, rs, imm);
} else {
/* ADDI32 */
mips32_op = OPC_ADDI;
goto do_addi;
}
break;
case ADDIU32: case ADDIU32:
mips32_op = OPC_ADDIU; mips32_op = OPC_ADDIU;
do_addi: do_addi:
@ -15059,8 +15067,28 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
do_cop1: do_cop1:
gen_cop1_ldst(ctx, mips32_op, rt, rs, imm); gen_cop1_ldst(ctx, mips32_op, rt, rs, imm);
break; break;
case ADDIUPC: case ADDIUPC: /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */
{ if (ctx->insn_flags & ISA_MIPS32R6) {
/* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */
switch ((ctx->opcode >> 16) & 0x1f) {
case ADDIUPC_00 ... ADDIUPC_07:
gen_pcrel(ctx, OPC_ADDIUPC, ctx->pc & ~0x3, rt);
break;
case AUIPC:
gen_pcrel(ctx, OPC_AUIPC, ctx->pc, rt);
break;
case ALUIPC:
gen_pcrel(ctx, OPC_ALUIPC, ctx->pc, rt);
break;
case LWPC_08 ... LWPC_0F:
gen_pcrel(ctx, R6_OPC_LWPC, ctx->pc & ~0x3, rt);
break;
default:
generate_exception(ctx, EXCP_RI);
break;
}
} else {
/* ADDIUPC */
int reg = mmreg(ZIMM(ctx->opcode, 23, 3)); int reg = mmreg(ZIMM(ctx->opcode, 23, 3));
int offset = SIMM(ctx->opcode, 0, 23) << 2; int offset = SIMM(ctx->opcode, 0, 23) << 2;
@ -20128,7 +20156,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pat
break; break;
case OPC_PCREL: case OPC_PCREL:
check_insn(ctx, ISA_MIPS32R6); check_insn(ctx, ISA_MIPS32R6);
gen_pcrel(ctx, rs, imm); gen_pcrel(ctx, ctx->opcode, ctx->pc, rs);
break; break;
default: /* Invalid */ default: /* Invalid */
MIPS_INVAL("major opcode"); MIPS_INVAL("major opcode");