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target/arm: Convert simple fp Neon 2-reg-misc insns

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Convert the Neon 2-reg-misc insns which are implemented with
simple calls to functions that take the input, output and
fpstatus pointer.

Backports commit 3e96b205286dfb8bbf363229709e4f8648fce379 from qemu
This commit is contained in:
Peter Maydell 2021-02-25 12:56:27 -05:00 committed by Lioncash
parent 3dcee11013
commit 6eb852ec1c
4 changed files with 79 additions and 49 deletions
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8
qemu/target/arm/neon-dp.decode
View file

@ -497,11 +497,19 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
SHA1SU1 1111 001 11 . 11 .. 10 .... 0 0111 0 . 0 .... @2misc_q1 SHA1SU1 1111 001 11 . 11 .. 10 .... 0 0111 0 . 0 .... @2misc_q1
SHA256SU0 1111 001 11 . 11 .. 10 .... 0 0111 1 . 0 .... @2misc_q1 SHA256SU0 1111 001 11 . 11 .. 10 .... 0 0111 1 . 0 .... @2misc_q1
VRINTX 1111 001 11 . 11 .. 10 .... 0 1001 . . 0 .... @2misc
VCVT_F16_F32 1111 001 11 . 11 .. 10 .... 0 1100 0 . 0 .... @2misc_q0 VCVT_F16_F32 1111 001 11 . 11 .. 10 .... 0 1100 0 . 0 .... @2misc_q0
VCVT_F32_F16 1111 001 11 . 11 .. 10 .... 0 1110 0 . 0 .... @2misc_q0 VCVT_F32_F16 1111 001 11 . 11 .. 10 .... 0 1110 0 . 0 .... @2misc_q0
VRECPE 1111 001 11 . 11 .. 11 .... 0 1000 . . 0 .... @2misc VRECPE 1111 001 11 . 11 .. 11 .... 0 1000 . . 0 .... @2misc
VRSQRTE 1111 001 11 . 11 .. 11 .... 0 1001 . . 0 .... @2misc VRSQRTE 1111 001 11 . 11 .. 11 .... 0 1001 . . 0 .... @2misc
VRECPE_F 1111 001 11 . 11 .. 11 .... 0 1010 . . 0 .... @2misc
VRSQRTE_F 1111 001 11 . 11 .. 11 .... 0 1011 . . 0 .... @2misc
VCVT_FS 1111 001 11 . 11 .. 11 .... 0 1100 . . 0 .... @2misc
VCVT_FU 1111 001 11 . 11 .. 11 .... 0 1101 . . 0 .... @2misc
VCVT_SF 1111 001 11 . 11 .. 11 .... 0 1110 . . 0 .... @2misc
VCVT_UF 1111 001 11 . 11 .. 11 .... 0 1111 . . 0 .... @2misc
] ]
# Subgroup for size != 0b11 # Subgroup for size != 0b11

63
qemu/target/arm/translate-neon.inc.c
View file

@ -3752,3 +3752,66 @@ static bool trans_VQNEG(DisasContext *s, arg_2misc *a)
}; };
return do_2misc(s, a, fn[a->size]); return do_2misc(s, a, fn[a->size]);
} }
static bool do_2misc_fp(DisasContext *s, arg_2misc *a,
NeonGenOneSingleOpFn *fn)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
int pass;
TCGv_ptr fpst;
/* Handle a 2-reg-misc operation by iterating 32 bits at a time */
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
return false;
}
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) &&
((a->vd | a->vm) & 0x10)) {
return false;
}
if (a->size != 2) {
/* TODO: FP16 will be the size == 1 case */
return false;
}
if ((a->vd | a->vm) & a->q) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
fpst = get_fpstatus_ptr(tcg_ctx, 1);
for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
TCGv_i32 tmp = neon_load_reg(s, a->vm, pass);
fn(tcg_ctx, tmp, tmp, fpst);
neon_store_reg(s, a->vd, pass, tmp);
}
tcg_temp_free_ptr(tcg_ctx, fpst);
return true;
}
#define DO_2MISC_FP(INSN, FUNC) \
static bool trans_##INSN(DisasContext *s, arg_2misc *a) \
{ \
return do_2misc_fp(s, a, FUNC); \
}
DO_2MISC_FP(VRECPE_F, gen_helper_recpe_f32)
DO_2MISC_FP(VRSQRTE_F, gen_helper_rsqrte_f32)
DO_2MISC_FP(VCVT_FS, gen_helper_vfp_sitos)
DO_2MISC_FP(VCVT_FU, gen_helper_vfp_uitos)
DO_2MISC_FP(VCVT_SF, gen_helper_vfp_tosizs)
DO_2MISC_FP(VCVT_UF, gen_helper_vfp_touizs)
static bool trans_VRINTX(DisasContext *s, arg_2misc *a)
{
if (!arm_dc_feature(s, ARM_FEATURE_V8)) {
return false;
}
return do_2misc_fp(s, a, gen_helper_rints_exact);
}

56
qemu/target/arm/translate.c
View file

@ -5049,6 +5049,13 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
case NEON_2RM_VRSQRTE: case NEON_2RM_VRSQRTE:
case NEON_2RM_VQABS: case NEON_2RM_VQABS:
case NEON_2RM_VQNEG: case NEON_2RM_VQNEG:
case NEON_2RM_VRECPE_F:
case NEON_2RM_VRSQRTE_F:
case NEON_2RM_VCVT_FS:
case NEON_2RM_VCVT_FU:
case NEON_2RM_VCVT_SF:
case NEON_2RM_VCVT_UF:
case NEON_2RM_VRINTX:
/* handled by decodetree */ /* handled by decodetree */
return 1; return 1;
case NEON_2RM_VTRN: case NEON_2RM_VTRN:
@ -5154,13 +5161,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
tcg_temp_free_i32(tcg_ctx, tcg_rmode); tcg_temp_free_i32(tcg_ctx, tcg_rmode);
break; break;
} }
case NEON_2RM_VRINTX:
{
TCGv_ptr fpstatus = get_fpstatus_ptr(tcg_ctx, 1);
gen_helper_rints_exact(tcg_ctx, tmp, tmp, fpstatus);
tcg_temp_free_ptr(tcg_ctx, fpstatus);
break;
}
case NEON_2RM_VCVTAU: case NEON_2RM_VCVTAU:
case NEON_2RM_VCVTAS: case NEON_2RM_VCVTAS:
case NEON_2RM_VCVTNU: case NEON_2RM_VCVTNU:
@ -5195,48 +5195,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
tcg_temp_free_ptr(tcg_ctx, fpst); tcg_temp_free_ptr(tcg_ctx, fpst);
break; break;
} }
case NEON_2RM_VRECPE_F:
{
TCGv_ptr fpstatus = get_fpstatus_ptr(tcg_ctx, 1);
gen_helper_recpe_f32(tcg_ctx, tmp, tmp, fpstatus);
tcg_temp_free_ptr(tcg_ctx, fpstatus);
break;
}
case NEON_2RM_VRSQRTE_F:
{
TCGv_ptr fpstatus = get_fpstatus_ptr(tcg_ctx, 1);
gen_helper_rsqrte_f32(tcg_ctx, tmp, tmp, fpstatus);
tcg_temp_free_ptr(tcg_ctx, fpstatus);
break;
}
case NEON_2RM_VCVT_FS: /* VCVT.F32.S32 */
{
TCGv_ptr fpstatus = get_fpstatus_ptr(tcg_ctx, 1);
gen_helper_vfp_sitos(tcg_ctx, tmp, tmp, fpstatus);
tcg_temp_free_ptr(tcg_ctx, fpstatus);
break;
}
case NEON_2RM_VCVT_FU: /* VCVT.F32.U32 */
{
TCGv_ptr fpstatus = get_fpstatus_ptr(tcg_ctx, 1);
gen_helper_vfp_uitos(tcg_ctx, tmp, tmp, fpstatus);
tcg_temp_free_ptr(tcg_ctx, fpstatus);
break;
}
case NEON_2RM_VCVT_SF: /* VCVT.S32.F32 */
{
TCGv_ptr fpstatus = get_fpstatus_ptr(tcg_ctx, 1);
gen_helper_vfp_tosizs(tcg_ctx, tmp, tmp, fpstatus);
tcg_temp_free_ptr(tcg_ctx, fpstatus);
break;
}
case NEON_2RM_VCVT_UF: /* VCVT.U32.F32 */
{
TCGv_ptr fpstatus = get_fpstatus_ptr(tcg_ctx, 1);
gen_helper_vfp_touizs(tcg_ctx, tmp, tmp, fpstatus);
tcg_temp_free_ptr(tcg_ctx, fpstatus);
break;
}
default: default:
/* Reserved op values were caught by the /* Reserved op values were caught by the
* neon_2rm_sizes[] check earlier. * neon_2rm_sizes[] check earlier.

1
qemu/target/arm/translate.h
View file

@ -380,6 +380,7 @@ typedef void NeonGenNarrowFn(TCGContext *t, TCGv_i32, TCGv_i64);
typedef void NeonGenNarrowEnvFn(TCGContext *t, TCGv_i32, TCGv_ptr, TCGv_i64); typedef void NeonGenNarrowEnvFn(TCGContext *t, TCGv_i32, TCGv_ptr, TCGv_i64);
typedef void NeonGenWidenFn(TCGContext *t, TCGv_i64, TCGv_i32); typedef void NeonGenWidenFn(TCGContext *t, TCGv_i64, TCGv_i32);
typedef void NeonGenTwoOpWidenFn(TCGContext *t, TCGv_i64, TCGv_i32, TCGv_i32); typedef void NeonGenTwoOpWidenFn(TCGContext *t, TCGv_i64, TCGv_i32, TCGv_i32);
typedef void NeonGenOneSingleOpFn(TCGContext *t, TCGv_i32, TCGv_i32, TCGv_ptr);
typedef void NeonGenTwoSingleOpFn(TCGContext *t, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); typedef void NeonGenTwoSingleOpFn(TCGContext *t, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
typedef void NeonGenTwoDoubleOpFn(TCGContext *t, TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); typedef void NeonGenTwoDoubleOpFn(TCGContext *t, TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
typedef void NeonGenOne64OpFn(TCGContext *t, TCGv_i64, TCGv_i64); typedef void NeonGenOne64OpFn(TCGContext *t, TCGv_i64, TCGv_i64);