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target/arm: Convert VFP VLDR and VSTR to decodetree
Convert the VFP single load/store insns VLDR and VSTR to decodetree. Backports commit 79b02a3b5231c5b8cd31e50cd549968dd0a05c49 from qemu
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parent
fe98885ff2
commit
6f0633ce80
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@ -866,3 +866,78 @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_sp *a)
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return true;
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}
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static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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uint32_t offset;
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TCGv_i32 addr;
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if (!vfp_access_check(s)) {
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return true;
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}
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offset = a->imm << 2;
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if (!a->u) {
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offset = -offset;
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}
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if (s->thumb && a->rn == 15) {
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/* This is actually UNPREDICTABLE */
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addr = tcg_temp_new_i32(tcg_ctx);
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tcg_gen_movi_i32(tcg_ctx, addr, s->pc & ~2);
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} else {
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addr = load_reg(s, a->rn);
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}
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tcg_gen_addi_i32(tcg_ctx, addr, addr, offset);
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if (a->l) {
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gen_vfp_ld(s, false, addr);
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gen_mov_vreg_F0(s, false, a->vd);
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} else {
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gen_mov_F0_vreg(s, false, a->vd);
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gen_vfp_st(s, false, addr);
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}
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tcg_temp_free_i32(tcg_ctx, addr);
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return true;
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}
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static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_sp *a)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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uint32_t offset;
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TCGv_i32 addr;
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/* UNDEF accesses to D16-D31 if they don't exist */
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if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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offset = a->imm << 2;
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if (!a->u) {
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offset = -offset;
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}
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if (s->thumb && a->rn == 15) {
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/* This is actually UNPREDICTABLE */
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addr = tcg_temp_new_i32(tcg_ctx);
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tcg_gen_movi_i32(tcg_ctx, addr, s->pc & ~2);
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} else {
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addr = load_reg(s, a->rn);
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}
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tcg_gen_addi_i32(tcg_ctx, addr, addr, offset);
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if (a->l) {
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gen_vfp_ld(s, true, addr);
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gen_mov_vreg_F0(s, true, a->vd);
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} else {
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gen_mov_F0_vreg(s, true, a->vd);
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gen_vfp_st(s, true, addr);
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}
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tcg_temp_free_i32(tcg_ctx, addr);
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return true;
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}
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@ -3817,26 +3817,8 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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else
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rd = VFP_SREG_D(insn);
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if ((insn & 0x01200000) == 0x01000000) {
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/* Single load/store */
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offset = (insn & 0xff) << 2;
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if ((insn & (1 << 23)) == 0)
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offset = 0-offset;
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if (s->thumb && rn == 15) {
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/* This is actually UNPREDICTABLE */
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addr = tcg_temp_new_i32(tcg_ctx);
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tcg_gen_movi_i32(tcg_ctx, addr, s->pc & ~2);
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} else {
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addr = load_reg(s, rn);
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}
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tcg_gen_addi_i32(tcg_ctx, addr, addr, offset);
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if (insn & (1 << 20)) {
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gen_vfp_ld(s, dp, addr);
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gen_mov_vreg_F0(s, dp, rd);
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} else {
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gen_mov_F0_vreg(s, dp, rd);
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gen_vfp_st(s, dp, addr);
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}
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tcg_temp_free_i32(tcg_ctx, addr);
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/* Already handled by decodetree */
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return 1;
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} else {
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/* load/store multiple */
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int w = insn & (1 << 21);
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@ -71,3 +71,10 @@ VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... \
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vm=%vm_sp
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VMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... \
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vm=%vm_dp
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# Note that the half-precision variants of VLDR and VSTR are
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# not part of this decodetree at all because they have bits [9:8] == 0b01
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VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 \
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vd=%vd_sp
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VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 \
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vd=%vd_dp
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