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target/mips: Add fields for SAARI and SAAR CP0 registers

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Add fields for SAARI and SAAR CP0 registers.

Backports commit 167db30e981cd72bef15182178037e51afc8e40d from qemu
This commit is contained in:
Yongbok Kim 2019-01-22 19:40:23 -05:00 committed by Lioncash
parent c0125e41a1
commit 6f850b88e4
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 8 additions and 2 deletions
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10
qemu/target/mips/cpu.h
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@ -164,8 +164,8 @@ typedef struct mips_def_t mips_def_t;
* 3 BadInstrX
* 4 GuestCtl1 GuestCtl0Ext
* 5 GuestCtl2
* 6 GuestCtl3
* 7
* 6 SAARI GuestCtl3
* 7 SAAR
*
*
* Register 12 Register 13 Register 14 Register 15
@ -546,6 +546,12 @@ struct CPUMIPSState {
* CP0 Register 9
*/
int32_t CP0_Count;
uint32_t CP0_SAARI;
#define CP0SAARI_TARGET 0 /* 5..0 */
uint64_t CP0_SAAR[2];
#define CP0SAAR_BASE 12 /* 43..12 */
#define CP0SAAR_SIZE 1 /* 5..1 */
#define CP0SAAR_EN 0
/*
* CP0 Register 10
*/