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target/riscv: Remove manual decoding from gen_branch()

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We now utilizes argument-sets of decodetree such that no manual
decoding is necessary.

Backports commit 090cc2c898a04e42350eabf1bcf7d245471603f9 from qemu
This commit is contained in:
Bastian Koppelmann 2019-03-19 04:59:05 -04:00 committed by Lioncash
parent 3fe4cf353c
commit 6f89816f5d
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 35 additions and 62 deletions
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49
qemu/target/riscv/insn_trans/trans_rvi.inc.c
View file

@ -50,7 +50,6 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
TCGLabel *misaligned = NULL;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(ctx, tcg_ctx->cpu_pc_risc, a->rs1);
tcg_gen_addi_tl(tcg_ctx, tcg_ctx->cpu_pc_risc, tcg_ctx->cpu_pc_risc, a->imm);
tcg_gen_andi_tl(tcg_ctx, tcg_ctx->cpu_pc_risc, tcg_ctx->cpu_pc_risc, (target_ulong)-2);
@ -76,41 +75,63 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
return true;
}
static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGLabel *l = gen_new_label(tcg_ctx);
TCGv source1, source2;
source1 = tcg_temp_new(tcg_ctx);
source2 = tcg_temp_new(tcg_ctx);
gen_get_gpr(ctx, source1, a->rs1);
gen_get_gpr(ctx, source2, a->rs2);
tcg_gen_brcond_tl(tcg_ctx, cond, source1, source2, l);
gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
gen_set_label(tcg_ctx, l); /* branch taken */
if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
/* misaligned */
gen_exception_inst_addr_mis(ctx);
} else {
gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
}
ctx->base.is_jmp = DISAS_NORETURN;
tcg_temp_free(tcg_ctx, source1);
tcg_temp_free(tcg_ctx, source2);
return true;
}
static bool trans_beq(DisasContext *ctx, arg_beq *a)
{
gen_branch(ctx, OPC_RISC_BEQ, a->rs1, a->rs2, a->imm);
return true;
return gen_branch(ctx, a, TCG_COND_EQ);
}
static bool trans_bne(DisasContext *ctx, arg_bne *a)
{
gen_branch(ctx, OPC_RISC_BNE, a->rs1, a->rs2, a->imm);
return true;
return gen_branch(ctx, a, TCG_COND_NE);
}
static bool trans_blt(DisasContext *ctx, arg_blt *a)
{
gen_branch(ctx, OPC_RISC_BLT, a->rs1, a->rs2, a->imm);
return true;
return gen_branch(ctx, a, TCG_COND_LT);
}
static bool trans_bge(DisasContext *ctx, arg_bge *a)
{
gen_branch(ctx, OPC_RISC_BGE, a->rs1, a->rs2, a->imm);
return true;
return gen_branch(ctx, a, TCG_COND_GE);
}
static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
{
gen_branch(ctx, OPC_RISC_BLTU, a->rs1, a->rs2, a->imm);
return true;
return gen_branch(ctx, a, TCG_COND_LTU);
}
static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
{
gen_branch(ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm);
return true;
return gen_branch(ctx, a, TCG_COND_GEU);
}
static bool trans_lb(DisasContext *ctx, arg_lb *a)

48
qemu/target/riscv/translate.c
View file

@ -547,54 +547,6 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
ctx->base.is_jmp = DISAS_NORETURN;
}
static void gen_branch(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
target_long bimm)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGLabel *l = gen_new_label(tcg_ctx);
TCGv source1, source2;
source1 = tcg_temp_new(tcg_ctx);
source2 = tcg_temp_new(tcg_ctx);
gen_get_gpr(ctx, source1, rs1);
gen_get_gpr(ctx, source2, rs2);
switch (opc) {
case OPC_RISC_BEQ:
tcg_gen_brcond_tl(tcg_ctx, TCG_COND_EQ, source1, source2, l);
break;
case OPC_RISC_BNE:
tcg_gen_brcond_tl(tcg_ctx, TCG_COND_NE, source1, source2, l);
break;
case OPC_RISC_BLT:
tcg_gen_brcond_tl(tcg_ctx, TCG_COND_LT, source1, source2, l);
break;
case OPC_RISC_BGE:
tcg_gen_brcond_tl(tcg_ctx, TCG_COND_GE, source1, source2, l);
break;
case OPC_RISC_BLTU:
tcg_gen_brcond_tl(tcg_ctx, TCG_COND_LTU, source1, source2, l);
break;
case OPC_RISC_BGEU:
tcg_gen_brcond_tl(tcg_ctx, TCG_COND_GEU, source1, source2, l);
break;
default:
gen_exception_illegal(ctx);
return;
}
tcg_temp_free(tcg_ctx, source1);
tcg_temp_free(tcg_ctx, source2);
gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
gen_set_label(tcg_ctx, l); /* branch taken */
if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) {
/* misaligned */
gen_exception_inst_addr_mis(ctx);
} else {
gen_goto_tb(ctx, 0, ctx->base.pc_next + bimm);
}
ctx->base.is_jmp = DISAS_NORETURN;
}
static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1,
target_long imm)
{