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target-mips: fix to clear MSACSR.Cause

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MSACSR.Cause bits are needed to be cleared before a vector floating-point
instructions.
FEXDO.df, FEXUPL.df and FEXUPR.df were missed out.

Backports commit d4f4f0d5d9e74c19614479592c8bc865d92773d0 from qemu
This commit is contained in:
Yongbok Kim 2018-02-14 16:59:06 -05:00 committed by Lioncash
parent 424b6eee4e
commit 6fac3fee4e
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 6 additions and 0 deletions
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6
qemu/target-mips/msa_helper.c
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@ -2639,6 +2639,8 @@ void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
wr_t *pwt = &(env->active_fpu.fpr[wt].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
uint32_t i; uint32_t i;
clear_msacsr_cause(env);
switch (df) { switch (df) {
case DF_WORD: case DF_WORD:
for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
@ -3189,6 +3191,8 @@ void helper_msa_fexupl_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pws = &(env->active_fpu.fpr[ws].wr);
uint32_t i; uint32_t i;
clear_msacsr_cause(env);
switch (df) { switch (df) {
case DF_WORD: case DF_WORD:
for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
@ -3221,6 +3225,8 @@ void helper_msa_fexupr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pws = &(env->active_fpu.fpr[ws].wr);
uint32_t i; uint32_t i;
clear_msacsr_cause(env);
switch (df) { switch (df) {
case DF_WORD: case DF_WORD:
for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {