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target/mips: Clean up handling of CP0 register 29

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Clean up handling of CP0 register 29.

Backports commit af4bb6da80d3f6c733055bb4e2a1b99a30e81d24 from qemu
This commit is contained in:
Aleksandar Markovic 2019-11-18 23:43:10 -05:00 committed by Lioncash
parent 7dc128c3ad
commit 6fae1432ce
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 46 additions and 40 deletions
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22
qemu/target/mips/cpu.h
View file

@ -232,12 +232,12 @@ typedef struct mips_def_t mips_def_t;
*
* 0 DataLo DataHi ErrorEPC DESAVE
* 1 TagLo TagHi
* 2 DataLo1 DataHi KScratch<n>
* 3 TagLo1 TagHi KScratch<n>
* 4 DataLo2 DataHi KScratch<n>
* 5 TagLo2 TagHi KScratch<n>
* 6 DataLo3 DataHi KScratch<n>
* 7 TagLo3 TagHi KScratch<n>
* 2 DataLo1 DataHi1 KScratch<n>
* 3 TagLo1 TagHi1 KScratch<n>
* 4 DataLo2 DataHi2 KScratch<n>
* 5 TagLo2 TagHi2 KScratch<n>
* 6 DataLo3 DataHi3 KScratch<n>
* 7 TagLo3 TagHi3 KScratch<n>
*
*/
#define CP0_REGISTER_00 0
@ -435,8 +435,14 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG28__TAGLO3 6
#define CP0_REG28__DATALO3 7
/* CP0 Register 29 */
#define CP0_REG29__IDATAHI 1
#define CP0_REG29__DDATAHI 3
#define CP0_REG29__TAGHI 0
#define CP0_REG29__DATAHI 1
#define CP0_REG29__TAGHI1 2
#define CP0_REG29__DATAHI1 3
#define CP0_REG29__TAGHI2 4
#define CP0_REG29__DATAHI2 5
#define CP0_REG29__TAGHI3 6
#define CP0_REG29__DATAHI3 7
/* CP0 Register 30 */
#define CP0_REG30__ERROREPC 0
/* CP0 Register 31 */

64
qemu/target/mips/translate.c
View file

@ -7580,17 +7580,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_29:
switch (sel) {
case 0:
case 2:
case 4:
case 6:
case CP0_REG29__TAGHI:
case CP0_REG29__TAGHI1:
case CP0_REG29__TAGHI2:
case CP0_REG29__TAGHI3:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_TagHi));
register_name = "TagHi";
break;
case 1:
case 3:
case 5:
case 7:
case CP0_REG29__DATAHI:
case CP0_REG29__DATAHI1:
case CP0_REG29__DATAHI2:
case CP0_REG29__DATAHI3:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_DataHi));
register_name = "DataHi";
break;
@ -8331,17 +8331,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_29:
switch (sel) {
case 0:
case 2:
case 4:
case 6:
case CP0_REG29__TAGHI:
case CP0_REG29__TAGHI1:
case CP0_REG29__TAGHI2:
case CP0_REG29__TAGHI3:
gen_helper_mtc0_taghi(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "TagHi";
break;
case 1:
case 3:
case 5:
case 7:
case CP0_REG29__DATAHI:
case CP0_REG29__DATAHI1:
case CP0_REG29__DATAHI2:
case CP0_REG29__DATAHI3:
gen_helper_mtc0_datahi(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "DataHi";
break;
@ -9055,17 +9055,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_29:
switch (sel) {
case 0:
case 2:
case 4:
case 6:
case CP0_REG29__TAGHI:
case CP0_REG29__TAGHI1:
case CP0_REG29__TAGHI2:
case CP0_REG29__TAGHI3:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_TagHi));
register_name = "TagHi";
break;
case 1:
case 3:
case 5:
case 7:
case CP0_REG29__DATAHI:
case CP0_REG29__DATAHI1:
case CP0_REG29__DATAHI2:
case CP0_REG29__DATAHI3:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_DataHi));
register_name = "DataHi";
break;
@ -9788,17 +9788,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_29:
switch (sel) {
case 0:
case 2:
case 4:
case 6:
case CP0_REG29__TAGHI:
case CP0_REG29__TAGHI1:
case CP0_REG29__TAGHI2:
case CP0_REG29__TAGHI3:
gen_helper_mtc0_taghi(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "TagHi";
break;
case 1:
case 3:
case 5:
case 7:
case CP0_REG29__DATAHI:
case CP0_REG29__DATAHI1:
case CP0_REG29__DATAHI2:
case CP0_REG29__DATAHI3:
gen_helper_mtc0_datahi(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "DataHi";
break;