mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2024-12-24 01:05:30 +00:00
target/mips: Move MXU_EN check one level higher
Move MXU_EN check to the main MXU decoding function, to avoid code repetition. Backports commit e5bf8a08293a1c576f8b6094f4deae7bdafceade from qemu
This commit is contained in:
parent
f2c3e173ad
commit
702abac53f
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@ -24251,23 +24251,16 @@ static void gen_mxu_s8ldd(DisasContext *ctx)
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{
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGv t0, t1;
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TCGv t0, t1;
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TCGLabel *l0;
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uint32_t XRa, Rb, s8, optn3;
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uint32_t XRa, Rb, s8, optn3;
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t0 = tcg_temp_new(tcg_ctx);
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t0 = tcg_temp_new(tcg_ctx);
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t1 = tcg_temp_new(tcg_ctx);
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t1 = tcg_temp_new(tcg_ctx);
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l0 = gen_new_label(tcg_ctx);
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XRa = extract32(ctx->opcode, 6, 4);
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XRa = extract32(ctx->opcode, 6, 4);
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s8 = extract32(ctx->opcode, 10, 8);
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s8 = extract32(ctx->opcode, 10, 8);
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optn3 = extract32(ctx->opcode, 18, 3);
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optn3 = extract32(ctx->opcode, 18, 3);
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Rb = extract32(ctx->opcode, 21, 5);
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Rb = extract32(ctx->opcode, 21, 5);
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gen_load_mxu_cr(ctx, t0);
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tcg_gen_andi_tl(tcg_ctx, t0, t0, MXU_CR_MXU_EN);
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tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_NE, t0, MXU_CR_MXU_EN, l0);
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gen_load_gpr(ctx, t0, Rb);
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gen_load_gpr(ctx, t0, Rb);
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tcg_gen_addi_tl(tcg_ctx, t0, t0, (int8_t)s8);
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tcg_gen_addi_tl(tcg_ctx, t0, t0, (int8_t)s8);
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@ -24325,8 +24318,6 @@ static void gen_mxu_s8ldd(DisasContext *ctx)
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gen_store_mxu_gpr(ctx, t0, XRa);
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gen_store_mxu_gpr(ctx, t0, XRa);
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gen_set_label(tcg_ctx, l0);
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tcg_temp_free(tcg_ctx, t0);
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tcg_temp_free(tcg_ctx, t0);
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tcg_temp_free(tcg_ctx, t1);
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tcg_temp_free(tcg_ctx, t1);
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}
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}
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@ -24338,7 +24329,6 @@ static void gen_mxu_d16mul(DisasContext *ctx)
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{
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGv t0, t1, t2, t3;
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TCGv t0, t1, t2, t3;
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TCGLabel *l0;
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uint32_t XRa, XRb, XRc, XRd, optn2;
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uint32_t XRa, XRb, XRc, XRd, optn2;
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t0 = tcg_temp_new(tcg_ctx);
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t0 = tcg_temp_new(tcg_ctx);
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@ -24346,18 +24336,12 @@ static void gen_mxu_d16mul(DisasContext *ctx)
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t2 = tcg_temp_new(tcg_ctx);
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t2 = tcg_temp_new(tcg_ctx);
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t3 = tcg_temp_new(tcg_ctx);
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t3 = tcg_temp_new(tcg_ctx);
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l0 = gen_new_label(tcg_ctx);
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XRa = extract32(ctx->opcode, 6, 4);
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XRa = extract32(ctx->opcode, 6, 4);
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XRb = extract32(ctx->opcode, 10, 4);
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XRb = extract32(ctx->opcode, 10, 4);
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XRc = extract32(ctx->opcode, 14, 4);
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XRc = extract32(ctx->opcode, 14, 4);
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XRd = extract32(ctx->opcode, 18, 4);
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XRd = extract32(ctx->opcode, 18, 4);
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optn2 = extract32(ctx->opcode, 22, 2);
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optn2 = extract32(ctx->opcode, 22, 2);
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gen_load_mxu_cr(ctx, t0);
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tcg_gen_andi_tl(tcg_ctx, t0, t0, MXU_CR_MXU_EN);
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tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_NE, t0, MXU_CR_MXU_EN, l0);
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gen_load_mxu_gpr(ctx, t1, XRb);
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gen_load_mxu_gpr(ctx, t1, XRb);
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tcg_gen_sextract_tl(tcg_ctx, t0, t1, 0, 16);
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tcg_gen_sextract_tl(tcg_ctx, t0, t1, 0, 16);
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tcg_gen_sextract_tl(tcg_ctx, t1, t1, 16, 16);
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tcg_gen_sextract_tl(tcg_ctx, t1, t1, 16, 16);
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@ -24386,8 +24370,6 @@ static void gen_mxu_d16mul(DisasContext *ctx)
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gen_store_mxu_gpr(ctx, t3, XRa);
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gen_store_mxu_gpr(ctx, t3, XRa);
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gen_store_mxu_gpr(ctx, t2, XRd);
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gen_store_mxu_gpr(ctx, t2, XRd);
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gen_set_label(tcg_ctx, l0);
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tcg_temp_free(tcg_ctx, t0);
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tcg_temp_free(tcg_ctx, t0);
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tcg_temp_free(tcg_ctx, t1);
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tcg_temp_free(tcg_ctx, t1);
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tcg_temp_free(tcg_ctx, t2);
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tcg_temp_free(tcg_ctx, t2);
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@ -24402,7 +24384,6 @@ static void gen_mxu_d16mac(DisasContext *ctx)
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{
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGv t0, t1, t2, t3;
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TCGv t0, t1, t2, t3;
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TCGLabel *l0;
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uint32_t XRa, XRb, XRc, XRd, optn2, aptn2;
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uint32_t XRa, XRb, XRc, XRd, optn2, aptn2;
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t0 = tcg_temp_new(tcg_ctx);
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t0 = tcg_temp_new(tcg_ctx);
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@ -24410,8 +24391,6 @@ static void gen_mxu_d16mac(DisasContext *ctx)
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t2 = tcg_temp_new(tcg_ctx);
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t2 = tcg_temp_new(tcg_ctx);
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t3 = tcg_temp_new(tcg_ctx);
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t3 = tcg_temp_new(tcg_ctx);
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l0 = gen_new_label(tcg_ctx);
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XRa = extract32(ctx->opcode, 6, 4);
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XRa = extract32(ctx->opcode, 6, 4);
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XRb = extract32(ctx->opcode, 10, 4);
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XRb = extract32(ctx->opcode, 10, 4);
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XRc = extract32(ctx->opcode, 14, 4);
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XRc = extract32(ctx->opcode, 14, 4);
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@ -24419,10 +24398,6 @@ static void gen_mxu_d16mac(DisasContext *ctx)
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optn2 = extract32(ctx->opcode, 22, 2);
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optn2 = extract32(ctx->opcode, 22, 2);
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aptn2 = extract32(ctx->opcode, 24, 2);
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aptn2 = extract32(ctx->opcode, 24, 2);
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gen_load_mxu_cr(ctx, t0);
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tcg_gen_andi_tl(tcg_ctx, t0, t0, MXU_CR_MXU_EN);
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tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_NE, t0, MXU_CR_MXU_EN, l0);
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gen_load_mxu_gpr(ctx, t1, XRb);
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gen_load_mxu_gpr(ctx, t1, XRb);
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tcg_gen_sextract_tl(tcg_ctx, t0, t1, 0, 16);
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tcg_gen_sextract_tl(tcg_ctx, t0, t1, 0, 16);
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tcg_gen_sextract_tl(tcg_ctx, t1, t1, 16, 16);
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tcg_gen_sextract_tl(tcg_ctx, t1, t1, 16, 16);
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@ -24473,8 +24448,6 @@ static void gen_mxu_d16mac(DisasContext *ctx)
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gen_store_mxu_gpr(ctx, t3, XRa);
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gen_store_mxu_gpr(ctx, t3, XRa);
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gen_store_mxu_gpr(ctx, t2, XRd);
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gen_store_mxu_gpr(ctx, t2, XRd);
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gen_set_label(tcg_ctx, l0);
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tcg_temp_free(tcg_ctx, t0);
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tcg_temp_free(tcg_ctx, t0);
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tcg_temp_free(tcg_ctx, t1);
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tcg_temp_free(tcg_ctx, t1);
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tcg_temp_free(tcg_ctx, t2);
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tcg_temp_free(tcg_ctx, t2);
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@ -24489,7 +24462,6 @@ static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx)
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{
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGv t0, t1, t2, t3, t4, t5, t6, t7;
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TCGv t0, t1, t2, t3, t4, t5, t6, t7;
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TCGLabel *l0;
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uint32_t XRa, XRb, XRc, XRd, sel;
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uint32_t XRa, XRb, XRc, XRd, sel;
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t0 = tcg_temp_new(tcg_ctx);
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t0 = tcg_temp_new(tcg_ctx);
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@ -24501,18 +24473,12 @@ static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx)
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t6 = tcg_temp_new(tcg_ctx);
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t6 = tcg_temp_new(tcg_ctx);
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t7 = tcg_temp_new(tcg_ctx);
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t7 = tcg_temp_new(tcg_ctx);
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l0 = gen_new_label(tcg_ctx);
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XRa = extract32(ctx->opcode, 6, 4);
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XRa = extract32(ctx->opcode, 6, 4);
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XRb = extract32(ctx->opcode, 10, 4);
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XRb = extract32(ctx->opcode, 10, 4);
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XRc = extract32(ctx->opcode, 14, 4);
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XRc = extract32(ctx->opcode, 14, 4);
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XRd = extract32(ctx->opcode, 18, 4);
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XRd = extract32(ctx->opcode, 18, 4);
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sel = extract32(ctx->opcode, 22, 2);
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sel = extract32(ctx->opcode, 22, 2);
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gen_load_mxu_cr(ctx, t0);
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tcg_gen_andi_tl(tcg_ctx, t0, t0, MXU_CR_MXU_EN);
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tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_NE, t0, MXU_CR_MXU_EN, l0);
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gen_load_mxu_gpr(ctx, t3, XRb);
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gen_load_mxu_gpr(ctx, t3, XRb);
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gen_load_mxu_gpr(ctx, t7, XRc);
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gen_load_mxu_gpr(ctx, t7, XRc);
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@ -24563,8 +24529,6 @@ static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx)
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gen_store_mxu_gpr(ctx, t0, XRd);
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gen_store_mxu_gpr(ctx, t0, XRd);
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gen_store_mxu_gpr(ctx, t1, XRa);
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gen_store_mxu_gpr(ctx, t1, XRa);
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gen_set_label(tcg_ctx, l0);
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tcg_temp_free(tcg_ctx, t0);
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tcg_temp_free(tcg_ctx, t0);
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tcg_temp_free(tcg_ctx, t1);
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tcg_temp_free(tcg_ctx, t1);
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tcg_temp_free(tcg_ctx, t2);
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tcg_temp_free(tcg_ctx, t2);
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@ -24583,23 +24547,16 @@ static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx)
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{
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGv t0, t1;
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TCGv t0, t1;
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TCGLabel *l0;
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uint32_t XRa, Rb, s12, sel;
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uint32_t XRa, Rb, s12, sel;
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t0 = tcg_temp_new(tcg_ctx);
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t0 = tcg_temp_new(tcg_ctx);
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t1 = tcg_temp_new(tcg_ctx);
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t1 = tcg_temp_new(tcg_ctx);
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l0 = gen_new_label(tcg_ctx);
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XRa = extract32(ctx->opcode, 6, 4);
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XRa = extract32(ctx->opcode, 6, 4);
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s12 = extract32(ctx->opcode, 10, 10);
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s12 = extract32(ctx->opcode, 10, 10);
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sel = extract32(ctx->opcode, 20, 1);
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sel = extract32(ctx->opcode, 20, 1);
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Rb = extract32(ctx->opcode, 21, 5);
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Rb = extract32(ctx->opcode, 21, 5);
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gen_load_mxu_cr(ctx, t0);
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tcg_gen_andi_tl(tcg_ctx, t0, t0, MXU_CR_MXU_EN);
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tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_NE, t0, MXU_CR_MXU_EN, l0);
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gen_load_gpr(ctx, t0, Rb);
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gen_load_gpr(ctx, t0, Rb);
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tcg_gen_movi_tl(tcg_ctx, t1, s12);
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tcg_gen_movi_tl(tcg_ctx, t1, s12);
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@ -24616,8 +24573,6 @@ static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx)
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}
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}
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gen_store_mxu_gpr(ctx, t1, XRa);
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gen_store_mxu_gpr(ctx, t1, XRa);
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gen_set_label(tcg_ctx, l0);
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tcg_temp_free(tcg_ctx, t0);
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tcg_temp_free(tcg_ctx, t0);
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tcg_temp_free(tcg_ctx, t1);
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tcg_temp_free(tcg_ctx, t1);
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}
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}
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@ -25513,6 +25468,7 @@ static void decode_opc_mxu__pool20(CPUMIPSState *env, DisasContext *ctx)
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*/
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*/
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static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
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static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
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{
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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/*
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/*
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* TODO: Investigate necessity of including handling of
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* TODO: Investigate necessity of including handling of
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* CLZ, CLO, SDBB in this function, as they belong to
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* CLZ, CLO, SDBB in this function, as they belong to
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@ -25543,232 +25499,244 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
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return;
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return;
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}
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}
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switch (opcode) {
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{
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case OPC_MXU_S32MADD:
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TCGv t_mxu_cr = tcg_temp_new(tcg_ctx);
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/* TODO: Implement emulation of S32MADD instruction. */
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TCGLabel *l_exit = gen_new_label(tcg_ctx);
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MIPS_INVAL("OPC_MXU_S32MADD");
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generate_exception_end(ctx, EXCP_RI);
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gen_load_mxu_cr(ctx, t_mxu_cr);
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break;
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tcg_gen_andi_tl(tcg_ctx, t_mxu_cr, t_mxu_cr, MXU_CR_MXU_EN);
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case OPC_MXU_S32MADDU:
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tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_NE, t_mxu_cr, MXU_CR_MXU_EN, l_exit);
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/* TODO: Implement emulation of S32MADDU instruction. */
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MIPS_INVAL("OPC_MXU_S32MADDU");
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switch (opcode) {
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generate_exception_end(ctx, EXCP_RI);
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case OPC_MXU_S32MADD:
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break;
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/* TODO: Implement emulation of S32MADD instruction. */
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case OPC_MXU__POOL00:
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MIPS_INVAL("OPC_MXU_S32MADD");
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decode_opc_mxu__pool00(env, ctx);
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generate_exception_end(ctx, EXCP_RI);
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break;
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break;
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case OPC_MXU_S32MSUB:
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case OPC_MXU_S32MADDU:
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/* TODO: Implement emulation of S32MSUB instruction. */
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/* TODO: Implement emulation of S32MADDU instruction. */
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MIPS_INVAL("OPC_MXU_S32MSUB");
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MIPS_INVAL("OPC_MXU_S32MADDU");
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generate_exception_end(ctx, EXCP_RI);
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generate_exception_end(ctx, EXCP_RI);
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break;
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break;
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case OPC_MXU_S32MSUBU:
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case OPC_MXU__POOL00:
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/* TODO: Implement emulation of S32MSUBU instruction. */
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decode_opc_mxu__pool00(env, ctx);
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MIPS_INVAL("OPC_MXU_S32MSUBU");
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break;
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generate_exception_end(ctx, EXCP_RI);
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case OPC_MXU_S32MSUB:
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break;
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/* TODO: Implement emulation of S32MSUB instruction. */
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case OPC_MXU__POOL01:
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MIPS_INVAL("OPC_MXU_S32MSUB");
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decode_opc_mxu__pool01(env, ctx);
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generate_exception_end(ctx, EXCP_RI);
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break;
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break;
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case OPC_MXU__POOL02:
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case OPC_MXU_S32MSUBU:
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decode_opc_mxu__pool02(env, ctx);
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/* TODO: Implement emulation of S32MSUBU instruction. */
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break;
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MIPS_INVAL("OPC_MXU_S32MSUBU");
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case OPC_MXU_D16MUL:
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generate_exception_end(ctx, EXCP_RI);
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gen_mxu_d16mul(ctx);
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break;
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break;
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case OPC_MXU__POOL01:
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case OPC_MXU__POOL03:
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decode_opc_mxu__pool01(env, ctx);
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decode_opc_mxu__pool03(env, ctx);
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break;
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break;
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case OPC_MXU__POOL02:
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case OPC_MXU_D16MAC:
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decode_opc_mxu__pool02(env, ctx);
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gen_mxu_d16mac(ctx);
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break;
|
||||||
break;
|
case OPC_MXU_D16MUL:
|
||||||
case OPC_MXU_D16MACF:
|
gen_mxu_d16mul(ctx);
|
||||||
/* TODO: Implement emulation of D16MACF instruction. */
|
break;
|
||||||
MIPS_INVAL("OPC_MXU_D16MACF");
|
case OPC_MXU__POOL03:
|
||||||
generate_exception_end(ctx, EXCP_RI);
|
decode_opc_mxu__pool03(env, ctx);
|
||||||
break;
|
break;
|
||||||
case OPC_MXU_D16MADL:
|
case OPC_MXU_D16MAC:
|
||||||
/* TODO: Implement emulation of D16MADL instruction. */
|
gen_mxu_d16mac(ctx);
|
||||||
MIPS_INVAL("OPC_MXU_D16MADL");
|
break;
|
||||||
generate_exception_end(ctx, EXCP_RI);
|
case OPC_MXU_D16MACF:
|
||||||
break;
|
/* TODO: Implement emulation of D16MACF instruction. */
|
||||||
case OPC_MXU_S16MAD:
|
MIPS_INVAL("OPC_MXU_D16MACF");
|
||||||
/* TODO: Implement emulation of S16MAD instruction. */
|
generate_exception_end(ctx, EXCP_RI);
|
||||||
MIPS_INVAL("OPC_MXU_S16MAD");
|
break;
|
||||||
generate_exception_end(ctx, EXCP_RI);
|
case OPC_MXU_D16MADL:
|
||||||
break;
|
/* TODO: Implement emulation of D16MADL instruction. */
|
||||||
case OPC_MXU_Q16ADD:
|
MIPS_INVAL("OPC_MXU_D16MADL");
|
||||||
/* TODO: Implement emulation of Q16ADD instruction. */
|
generate_exception_end(ctx, EXCP_RI);
|
||||||
MIPS_INVAL("OPC_MXU_Q16ADD");
|
break;
|
||||||
generate_exception_end(ctx, EXCP_RI);
|
case OPC_MXU_S16MAD:
|
||||||
break;
|
/* TODO: Implement emulation of S16MAD instruction. */
|
||||||
case OPC_MXU_D16MACE:
|
MIPS_INVAL("OPC_MXU_S16MAD");
|
||||||
/* TODO: Implement emulation of D16MACE instruction. */
|
generate_exception_end(ctx, EXCP_RI);
|
||||||
MIPS_INVAL("OPC_MXU_D16MACE");
|
break;
|
||||||
generate_exception_end(ctx, EXCP_RI);
|
case OPC_MXU_Q16ADD:
|
||||||
break;
|
/* TODO: Implement emulation of Q16ADD instruction. */
|
||||||
case OPC_MXU__POOL04:
|
MIPS_INVAL("OPC_MXU_Q16ADD");
|
||||||
decode_opc_mxu__pool04(env, ctx);
|
generate_exception_end(ctx, EXCP_RI);
|
||||||
break;
|
break;
|
||||||
case OPC_MXU__POOL05:
|
case OPC_MXU_D16MACE:
|
||||||
decode_opc_mxu__pool05(env, ctx);
|
/* TODO: Implement emulation of D16MACE instruction. */
|
||||||
break;
|
MIPS_INVAL("OPC_MXU_D16MACE");
|
||||||
case OPC_MXU__POOL06:
|
generate_exception_end(ctx, EXCP_RI);
|
||||||
decode_opc_mxu__pool06(env, ctx);
|
break;
|
||||||
break;
|
case OPC_MXU__POOL04:
|
||||||
case OPC_MXU__POOL07:
|
decode_opc_mxu__pool04(env, ctx);
|
||||||
decode_opc_mxu__pool07(env, ctx);
|
break;
|
||||||
break;
|
case OPC_MXU__POOL05:
|
||||||
case OPC_MXU__POOL08:
|
decode_opc_mxu__pool05(env, ctx);
|
||||||
decode_opc_mxu__pool08(env, ctx);
|
break;
|
||||||
break;
|
case OPC_MXU__POOL06:
|
||||||
case OPC_MXU__POOL09:
|
decode_opc_mxu__pool06(env, ctx);
|
||||||
decode_opc_mxu__pool09(env, ctx);
|
break;
|
||||||
break;
|
case OPC_MXU__POOL07:
|
||||||
case OPC_MXU__POOL10:
|
decode_opc_mxu__pool07(env, ctx);
|
||||||
decode_opc_mxu__pool10(env, ctx);
|
break;
|
||||||
break;
|
case OPC_MXU__POOL08:
|
||||||
case OPC_MXU__POOL11:
|
decode_opc_mxu__pool08(env, ctx);
|
||||||
decode_opc_mxu__pool11(env, ctx);
|
break;
|
||||||
break;
|
case OPC_MXU__POOL09:
|
||||||
case OPC_MXU_D32ADD:
|
decode_opc_mxu__pool09(env, ctx);
|
||||||
/* TODO: Implement emulation of D32ADD instruction. */
|
break;
|
||||||
MIPS_INVAL("OPC_MXU_D32ADD");
|
case OPC_MXU__POOL10:
|
||||||
generate_exception_end(ctx, EXCP_RI);
|
decode_opc_mxu__pool10(env, ctx);
|
||||||
break;
|
break;
|
||||||
case OPC_MXU__POOL12:
|
case OPC_MXU__POOL11:
|
||||||
decode_opc_mxu__pool12(env, ctx);
|
decode_opc_mxu__pool11(env, ctx);
|
||||||
break;
|
break;
|
||||||
case OPC_MXU__POOL13:
|
case OPC_MXU_D32ADD:
|
||||||
decode_opc_mxu__pool13(env, ctx);
|
/* TODO: Implement emulation of D32ADD instruction. */
|
||||||
break;
|
MIPS_INVAL("OPC_MXU_D32ADD");
|
||||||
case OPC_MXU__POOL14:
|
generate_exception_end(ctx, EXCP_RI);
|
||||||
decode_opc_mxu__pool14(env, ctx);
|
break;
|
||||||
break;
|
case OPC_MXU__POOL12:
|
||||||
case OPC_MXU_Q8ACCE:
|
decode_opc_mxu__pool12(env, ctx);
|
||||||
/* TODO: Implement emulation of Q8ACCE instruction. */
|
break;
|
||||||
MIPS_INVAL("OPC_MXU_Q8ACCE");
|
case OPC_MXU__POOL13:
|
||||||
generate_exception_end(ctx, EXCP_RI);
|
decode_opc_mxu__pool13(env, ctx);
|
||||||
break;
|
break;
|
||||||
case OPC_MXU_S8LDD:
|
case OPC_MXU__POOL14:
|
||||||
gen_mxu_s8ldd(ctx);
|
decode_opc_mxu__pool14(env, ctx);
|
||||||
break;
|
break;
|
||||||
case OPC_MXU_S8STD:
|
case OPC_MXU_Q8ACCE:
|
||||||
/* TODO: Implement emulation of S8STD instruction. */
|
/* TODO: Implement emulation of Q8ACCE instruction. */
|
||||||
MIPS_INVAL("OPC_MXU_S8STD");
|
MIPS_INVAL("OPC_MXU_Q8ACCE");
|
||||||
generate_exception_end(ctx, EXCP_RI);
|
generate_exception_end(ctx, EXCP_RI);
|
||||||
break;
|
break;
|
||||||
case OPC_MXU_S8LDI:
|
case OPC_MXU_S8LDD:
|
||||||
/* TODO: Implement emulation of S8LDI instruction. */
|
gen_mxu_s8ldd(ctx);
|
||||||
MIPS_INVAL("OPC_MXU_S8LDI");
|
break;
|
||||||
generate_exception_end(ctx, EXCP_RI);
|
case OPC_MXU_S8STD:
|
||||||
break;
|
/* TODO: Implement emulation of S8STD instruction. */
|
||||||
case OPC_MXU_S8SDI:
|
MIPS_INVAL("OPC_MXU_S8STD");
|
||||||
/* TODO: Implement emulation of S8SDI instruction. */
|
generate_exception_end(ctx, EXCP_RI);
|
||||||
MIPS_INVAL("OPC_MXU_S8SDI");
|
break;
|
||||||
generate_exception_end(ctx, EXCP_RI);
|
case OPC_MXU_S8LDI:
|
||||||
break;
|
/* TODO: Implement emulation of S8LDI instruction. */
|
||||||
case OPC_MXU__POOL15:
|
MIPS_INVAL("OPC_MXU_S8LDI");
|
||||||
decode_opc_mxu__pool15(env, ctx);
|
generate_exception_end(ctx, EXCP_RI);
|
||||||
break;
|
break;
|
||||||
case OPC_MXU__POOL16:
|
case OPC_MXU_S8SDI:
|
||||||
decode_opc_mxu__pool16(env, ctx);
|
/* TODO: Implement emulation of S8SDI instruction. */
|
||||||
break;
|
MIPS_INVAL("OPC_MXU_S8SDI");
|
||||||
case OPC_MXU_LXB:
|
generate_exception_end(ctx, EXCP_RI);
|
||||||
/* TODO: Implement emulation of LXB instruction. */
|
break;
|
||||||
MIPS_INVAL("OPC_MXU_LXB");
|
case OPC_MXU__POOL15:
|
||||||
generate_exception_end(ctx, EXCP_RI);
|
decode_opc_mxu__pool15(env, ctx);
|
||||||
break;
|
break;
|
||||||
case OPC_MXU_S16LDD:
|
case OPC_MXU__POOL16:
|
||||||
/* TODO: Implement emulation of S16LDD instruction. */
|
decode_opc_mxu__pool16(env, ctx);
|
||||||
MIPS_INVAL("OPC_MXU_S16LDD");
|
break;
|
||||||
generate_exception_end(ctx, EXCP_RI);
|
case OPC_MXU_LXB:
|
||||||
break;
|
/* TODO: Implement emulation of LXB instruction. */
|
||||||
case OPC_MXU_S16STD:
|
MIPS_INVAL("OPC_MXU_LXB");
|
||||||
/* TODO: Implement emulation of S16STD instruction. */
|
generate_exception_end(ctx, EXCP_RI);
|
||||||
MIPS_INVAL("OPC_MXU_S16STD");
|
break;
|
||||||
generate_exception_end(ctx, EXCP_RI);
|
case OPC_MXU_S16LDD:
|
||||||
break;
|
/* TODO: Implement emulation of S16LDD instruction. */
|
||||||
case OPC_MXU_S16LDI:
|
MIPS_INVAL("OPC_MXU_S16LDD");
|
||||||
/* TODO: Implement emulation of S16LDI instruction. */
|
generate_exception_end(ctx, EXCP_RI);
|
||||||
MIPS_INVAL("OPC_MXU_S16LDI");
|
break;
|
||||||
generate_exception_end(ctx, EXCP_RI);
|
case OPC_MXU_S16STD:
|
||||||
break;
|
/* TODO: Implement emulation of S16STD instruction. */
|
||||||
case OPC_MXU_S16SDI:
|
MIPS_INVAL("OPC_MXU_S16STD");
|
||||||
/* TODO: Implement emulation of S16SDI instruction. */
|
generate_exception_end(ctx, EXCP_RI);
|
||||||
MIPS_INVAL("OPC_MXU_S16SDI");
|
break;
|
||||||
generate_exception_end(ctx, EXCP_RI);
|
case OPC_MXU_S16LDI:
|
||||||
break;
|
/* TODO: Implement emulation of S16LDI instruction. */
|
||||||
case OPC_MXU_D32SLL:
|
MIPS_INVAL("OPC_MXU_S16LDI");
|
||||||
/* TODO: Implement emulation of D32SLL instruction. */
|
generate_exception_end(ctx, EXCP_RI);
|
||||||
MIPS_INVAL("OPC_MXU_D32SLL");
|
break;
|
||||||
generate_exception_end(ctx, EXCP_RI);
|
case OPC_MXU_S16SDI:
|
||||||
break;
|
/* TODO: Implement emulation of S16SDI instruction. */
|
||||||
case OPC_MXU_D32SLR:
|
MIPS_INVAL("OPC_MXU_S16SDI");
|
||||||
/* TODO: Implement emulation of D32SLR instruction. */
|
generate_exception_end(ctx, EXCP_RI);
|
||||||
MIPS_INVAL("OPC_MXU_D32SLR");
|
break;
|
||||||
generate_exception_end(ctx, EXCP_RI);
|
case OPC_MXU_D32SLL:
|
||||||
break;
|
/* TODO: Implement emulation of D32SLL instruction. */
|
||||||
case OPC_MXU_D32SARL:
|
MIPS_INVAL("OPC_MXU_D32SLL");
|
||||||
/* TODO: Implement emulation of D32SARL instruction. */
|
generate_exception_end(ctx, EXCP_RI);
|
||||||
MIPS_INVAL("OPC_MXU_D32SARL");
|
break;
|
||||||
generate_exception_end(ctx, EXCP_RI);
|
case OPC_MXU_D32SLR:
|
||||||
break;
|
/* TODO: Implement emulation of D32SLR instruction. */
|
||||||
case OPC_MXU_D32SAR:
|
MIPS_INVAL("OPC_MXU_D32SLR");
|
||||||
/* TODO: Implement emulation of D32SAR instruction. */
|
generate_exception_end(ctx, EXCP_RI);
|
||||||
MIPS_INVAL("OPC_MXU_D32SAR");
|
break;
|
||||||
generate_exception_end(ctx, EXCP_RI);
|
case OPC_MXU_D32SARL:
|
||||||
break;
|
/* TODO: Implement emulation of D32SARL instruction. */
|
||||||
case OPC_MXU_Q16SLL:
|
MIPS_INVAL("OPC_MXU_D32SARL");
|
||||||
/* TODO: Implement emulation of Q16SLL instruction. */
|
generate_exception_end(ctx, EXCP_RI);
|
||||||
MIPS_INVAL("OPC_MXU_Q16SLL");
|
break;
|
||||||
generate_exception_end(ctx, EXCP_RI);
|
case OPC_MXU_D32SAR:
|
||||||
break;
|
/* TODO: Implement emulation of D32SAR instruction. */
|
||||||
case OPC_MXU_Q16SLR:
|
MIPS_INVAL("OPC_MXU_D32SAR");
|
||||||
/* TODO: Implement emulation of Q16SLR instruction. */
|
generate_exception_end(ctx, EXCP_RI);
|
||||||
MIPS_INVAL("OPC_MXU_Q16SLR");
|
break;
|
||||||
generate_exception_end(ctx, EXCP_RI);
|
case OPC_MXU_Q16SLL:
|
||||||
break;
|
/* TODO: Implement emulation of Q16SLL instruction. */
|
||||||
case OPC_MXU__POOL17:
|
MIPS_INVAL("OPC_MXU_Q16SLL");
|
||||||
decode_opc_mxu__pool17(env, ctx);
|
generate_exception_end(ctx, EXCP_RI);
|
||||||
break;
|
break;
|
||||||
case OPC_MXU_Q16SAR:
|
case OPC_MXU_Q16SLR:
|
||||||
/* TODO: Implement emulation of Q16SAR instruction. */
|
/* TODO: Implement emulation of Q16SLR instruction. */
|
||||||
MIPS_INVAL("OPC_MXU_Q16SAR");
|
MIPS_INVAL("OPC_MXU_Q16SLR");
|
||||||
generate_exception_end(ctx, EXCP_RI);
|
generate_exception_end(ctx, EXCP_RI);
|
||||||
break;
|
break;
|
||||||
case OPC_MXU__POOL18:
|
case OPC_MXU__POOL17:
|
||||||
decode_opc_mxu__pool18(env, ctx);
|
decode_opc_mxu__pool17(env, ctx);
|
||||||
break;
|
break;
|
||||||
case OPC_MXU__POOL19:
|
case OPC_MXU_Q16SAR:
|
||||||
decode_opc_mxu__pool19(env, ctx);
|
/* TODO: Implement emulation of Q16SAR instruction. */
|
||||||
break;
|
MIPS_INVAL("OPC_MXU_Q16SAR");
|
||||||
case OPC_MXU__POOL20:
|
generate_exception_end(ctx, EXCP_RI);
|
||||||
decode_opc_mxu__pool20(env, ctx);
|
break;
|
||||||
break;
|
case OPC_MXU__POOL18:
|
||||||
case OPC_MXU_Q16SCOP:
|
decode_opc_mxu__pool18(env, ctx);
|
||||||
/* TODO: Implement emulation of Q16SCOP instruction. */
|
break;
|
||||||
MIPS_INVAL("OPC_MXU_Q16SCOP");
|
case OPC_MXU__POOL19:
|
||||||
generate_exception_end(ctx, EXCP_RI);
|
decode_opc_mxu__pool19(env, ctx);
|
||||||
break;
|
break;
|
||||||
case OPC_MXU_Q8MADL:
|
case OPC_MXU__POOL20:
|
||||||
/* TODO: Implement emulation of Q8MADL instruction. */
|
decode_opc_mxu__pool20(env, ctx);
|
||||||
MIPS_INVAL("OPC_MXU_Q8MADL");
|
break;
|
||||||
generate_exception_end(ctx, EXCP_RI);
|
case OPC_MXU_Q16SCOP:
|
||||||
break;
|
/* TODO: Implement emulation of Q16SCOP instruction. */
|
||||||
case OPC_MXU_S32SFL:
|
MIPS_INVAL("OPC_MXU_Q16SCOP");
|
||||||
/* TODO: Implement emulation of S32SFL instruction. */
|
generate_exception_end(ctx, EXCP_RI);
|
||||||
MIPS_INVAL("OPC_MXU_S32SFL");
|
break;
|
||||||
generate_exception_end(ctx, EXCP_RI);
|
case OPC_MXU_Q8MADL:
|
||||||
break;
|
/* TODO: Implement emulation of Q8MADL instruction. */
|
||||||
case OPC_MXU_Q8SAD:
|
MIPS_INVAL("OPC_MXU_Q8MADL");
|
||||||
/* TODO: Implement emulation of Q8SAD instruction. */
|
generate_exception_end(ctx, EXCP_RI);
|
||||||
MIPS_INVAL("OPC_MXU_Q8SAD");
|
break;
|
||||||
generate_exception_end(ctx, EXCP_RI);
|
case OPC_MXU_S32SFL:
|
||||||
break;
|
/* TODO: Implement emulation of S32SFL instruction. */
|
||||||
default:
|
MIPS_INVAL("OPC_MXU_S32SFL");
|
||||||
MIPS_INVAL("decode_opc_mxu");
|
generate_exception_end(ctx, EXCP_RI);
|
||||||
generate_exception_end(ctx, EXCP_RI);
|
break;
|
||||||
|
case OPC_MXU_Q8SAD:
|
||||||
|
/* TODO: Implement emulation of Q8SAD instruction. */
|
||||||
|
MIPS_INVAL("OPC_MXU_Q8SAD");
|
||||||
|
generate_exception_end(ctx, EXCP_RI);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
MIPS_INVAL("decode_opc_mxu");
|
||||||
|
generate_exception_end(ctx, EXCP_RI);
|
||||||
|
}
|
||||||
|
|
||||||
|
gen_set_label(tcg_ctx, l_exit);
|
||||||
|
tcg_temp_free(tcg_ctx, t_mxu_cr);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue