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target-mips: enable CM GCR in MIPS64R6-generic CPU

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Indicate that in the MIPS64R6-generic CPU the memory-mapped
Global Configuration Register Space is implemented.

Backports commit a9a95061715ca09abff56a3f239f704c410912c2 from qemu
This commit is contained in:
Leon Alrae 2018-02-22 10:46:29 -05:00 committed by Lioncash
parent d65583df80
commit 70306ec586
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 1 additions and 1 deletions
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2
qemu/target-mips/translate_init.c
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@ -783,7 +783,7 @@ static const mips_def_t mips_defs[] =
(2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
(0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
MIPS_CONFIG2,
MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
(1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
(1 << CP0C3_RXI) | (1 << CP0C3_LPA),
MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |