tcg: Implement insert_op_before

Rather reserving space in the op stream for optimization,
let the optimizer add ops as necessary.

Backports commit a4ce099a7a4b4734c372f6bf28f3362e370f23c1 from qemu

qemu/aarch64.h

@@ -2774,7 +2774,6 @@
 #define tcg_gen_nor_i64 tcg_gen_nor_i64_aarch64
 #define tcg_gen_not_i32 tcg_gen_not_i32_aarch64
 #define tcg_gen_not_i64 tcg_gen_not_i64_aarch64
-#define tcg_gen_op0 tcg_gen_op0_aarch64
 #define tcg_gen_op1 tcg_gen_op1_aarch64
 #define tcg_gen_op2 tcg_gen_op2_aarch64
 #define tcg_gen_op3 tcg_gen_op3_aarch64

qemu/aarch64eb.h

@@ -2774,7 +2774,6 @@
 #define tcg_gen_nor_i64 tcg_gen_nor_i64_aarch64eb
 #define tcg_gen_not_i32 tcg_gen_not_i32_aarch64eb
 #define tcg_gen_not_i64 tcg_gen_not_i64_aarch64eb
-#define tcg_gen_op0 tcg_gen_op0_aarch64eb
 #define tcg_gen_op1 tcg_gen_op1_aarch64eb
 #define tcg_gen_op2 tcg_gen_op2_aarch64eb
 #define tcg_gen_op3 tcg_gen_op3_aarch64eb

qemu/arm.h

@@ -2774,7 +2774,6 @@
 #define tcg_gen_nor_i64 tcg_gen_nor_i64_arm
 #define tcg_gen_not_i32 tcg_gen_not_i32_arm
 #define tcg_gen_not_i64 tcg_gen_not_i64_arm
-#define tcg_gen_op0 tcg_gen_op0_arm
 #define tcg_gen_op1 tcg_gen_op1_arm
 #define tcg_gen_op2 tcg_gen_op2_arm
 #define tcg_gen_op3 tcg_gen_op3_arm

qemu/armeb.h

@@ -2774,7 +2774,6 @@
 #define tcg_gen_nor_i64 tcg_gen_nor_i64_armeb
 #define tcg_gen_not_i32 tcg_gen_not_i32_armeb
 #define tcg_gen_not_i64 tcg_gen_not_i64_armeb
-#define tcg_gen_op0 tcg_gen_op0_armeb
 #define tcg_gen_op1 tcg_gen_op1_armeb
 #define tcg_gen_op2 tcg_gen_op2_armeb
 #define tcg_gen_op3 tcg_gen_op3_armeb

qemu/header_gen.py

@@ -2780,7 +2780,6 @@ symbols = (
     'tcg_gen_nor_i64',
     'tcg_gen_not_i32',
     'tcg_gen_not_i64',
-    'tcg_gen_op0',
     'tcg_gen_op1',
     'tcg_gen_op2',
     'tcg_gen_op3',

qemu/m68k.h

@@ -2774,7 +2774,6 @@
 #define tcg_gen_nor_i64 tcg_gen_nor_i64_m68k
 #define tcg_gen_not_i32 tcg_gen_not_i32_m68k
 #define tcg_gen_not_i64 tcg_gen_not_i64_m68k
-#define tcg_gen_op0 tcg_gen_op0_m68k
 #define tcg_gen_op1 tcg_gen_op1_m68k
 #define tcg_gen_op2 tcg_gen_op2_m68k
 #define tcg_gen_op3 tcg_gen_op3_m68k

qemu/mips.h

@@ -2774,7 +2774,6 @@
 #define tcg_gen_nor_i64 tcg_gen_nor_i64_mips
 #define tcg_gen_not_i32 tcg_gen_not_i32_mips
 #define tcg_gen_not_i64 tcg_gen_not_i64_mips
-#define tcg_gen_op0 tcg_gen_op0_mips
 #define tcg_gen_op1 tcg_gen_op1_mips
 #define tcg_gen_op2 tcg_gen_op2_mips
 #define tcg_gen_op3 tcg_gen_op3_mips

qemu/mips64.h

@@ -2774,7 +2774,6 @@
 #define tcg_gen_nor_i64 tcg_gen_nor_i64_mips64
 #define tcg_gen_not_i32 tcg_gen_not_i32_mips64
 #define tcg_gen_not_i64 tcg_gen_not_i64_mips64
-#define tcg_gen_op0 tcg_gen_op0_mips64
 #define tcg_gen_op1 tcg_gen_op1_mips64
 #define tcg_gen_op2 tcg_gen_op2_mips64
 #define tcg_gen_op3 tcg_gen_op3_mips64

qemu/mips64el.h

@@ -2774,7 +2774,6 @@
 #define tcg_gen_nor_i64 tcg_gen_nor_i64_mips64el
 #define tcg_gen_not_i32 tcg_gen_not_i32_mips64el
 #define tcg_gen_not_i64 tcg_gen_not_i64_mips64el
-#define tcg_gen_op0 tcg_gen_op0_mips64el
 #define tcg_gen_op1 tcg_gen_op1_mips64el
 #define tcg_gen_op2 tcg_gen_op2_mips64el
 #define tcg_gen_op3 tcg_gen_op3_mips64el

qemu/mipsel.h

@@ -2774,7 +2774,6 @@
 #define tcg_gen_nor_i64 tcg_gen_nor_i64_mipsel
 #define tcg_gen_not_i32 tcg_gen_not_i32_mipsel
 #define tcg_gen_not_i64 tcg_gen_not_i64_mipsel
-#define tcg_gen_op0 tcg_gen_op0_mipsel
 #define tcg_gen_op1 tcg_gen_op1_mipsel
 #define tcg_gen_op2 tcg_gen_op2_mipsel
 #define tcg_gen_op3 tcg_gen_op3_mipsel

qemu/powerpc.h

@@ -2774,7 +2774,6 @@
 #define tcg_gen_nor_i64 tcg_gen_nor_i64_powerpc
 #define tcg_gen_not_i32 tcg_gen_not_i32_powerpc
 #define tcg_gen_not_i64 tcg_gen_not_i64_powerpc
-#define tcg_gen_op0 tcg_gen_op0_powerpc
 #define tcg_gen_op1 tcg_gen_op1_powerpc
 #define tcg_gen_op2 tcg_gen_op2_powerpc
 #define tcg_gen_op3 tcg_gen_op3_powerpc

qemu/sparc.h

@@ -2774,7 +2774,6 @@
 #define tcg_gen_nor_i64 tcg_gen_nor_i64_sparc
 #define tcg_gen_not_i32 tcg_gen_not_i32_sparc
 #define tcg_gen_not_i64 tcg_gen_not_i64_sparc
-#define tcg_gen_op0 tcg_gen_op0_sparc
 #define tcg_gen_op1 tcg_gen_op1_sparc
 #define tcg_gen_op2 tcg_gen_op2_sparc
 #define tcg_gen_op3 tcg_gen_op3_sparc

qemu/sparc64.h

@@ -2774,7 +2774,6 @@
 #define tcg_gen_nor_i64 tcg_gen_nor_i64_sparc64
 #define tcg_gen_not_i32 tcg_gen_not_i32_sparc64
 #define tcg_gen_not_i64 tcg_gen_not_i64_sparc64
-#define tcg_gen_op0 tcg_gen_op0_sparc64
 #define tcg_gen_op1 tcg_gen_op1_sparc64
 #define tcg_gen_op2 tcg_gen_op2_sparc64
 #define tcg_gen_op3 tcg_gen_op3_sparc64

qemu/tcg/optimize.c

@@ -53,6 +53,38 @@ static void reset_temp(TCGContext *s, TCGArg temp)
     temps[temp].mask = -1;
 }
 
+static TCGOp *insert_op_before(TCGContext *s, TCGOp *old_op,
+                                TCGOpcode opc, int nargs)
+{
+    int oi = s->gen_next_op_idx;
+    int pi = s->gen_next_parm_idx;
+    int prev = old_op->prev;
+    int next = old_op - s->gen_op_buf;
+    TCGOp *new_op;
+    TCGOp new_opp = {0};
+
+    tcg_debug_assert(oi < OPC_BUF_SIZE);
+    tcg_debug_assert(pi + nargs <= OPPARAM_BUF_SIZE);
+    s->gen_next_op_idx = oi + 1;
+    s->gen_next_parm_idx = pi + nargs;
+
+    new_opp.opc = opc;
+    new_opp.args = pi;
+    new_opp.prev = prev;
+    new_opp.next = next;
+
+    new_op = &s->gen_op_buf[oi];
+    *new_op = new_opp;
+    if (prev >= 0) {
+        s->gen_op_buf[prev].next = oi;
+    } else {
+        s->gen_first_op_idx = oi;
+    }
+    old_op->prev = oi;
+
+    return new_op;
+}
+
 /* Reset all temporaries, given that there are NB_TEMPS of them.  */
 static void reset_all_temps(TCGContext *s, int nb_temps)
 {
@@ -1109,8 +1141,8 @@ static void tcg_constant_folding(TCGContext *s)
                 uint64_t a = ((uint64_t)ah << 32) | al;
                 uint64_t b = ((uint64_t)bh << 32) | bl;
                 TCGArg rl, rh;
-                TCGOp *op2;
+                TCGOp *op2 = insert_op_before(s, op, INDEX_op_movi_i32, 2);
-                TCGArg *args2;
+                TCGArg *args2 = &s->gen_opparam_buf[op2->args];
 
                 if (opc == INDEX_op_add2_i32) {
                     a += b;
@@ -1118,15 +1150,6 @@ static void tcg_constant_folding(TCGContext *s)
                     a -= b;
                 }
 
-                /* We emit the extra nop when we emit the add2/sub2.  */
-                op2 = &s->gen_op_buf[oi_next];
-                assert(op2->opc == INDEX_op_nop);
-
-                /* But we still have to allocate args for the op.  */
-                op2->args = s->gen_next_parm_idx;
-                s->gen_next_parm_idx += 2;
-                args2 = &s->gen_opparam_buf[op2->args];
-
                 rl = args[0];
                 rh = args[1];
                 tcg_opt_gen_movi(s, op, args, opc, rl, (uint32_t)a);
@@ -1145,17 +1168,8 @@ static void tcg_constant_folding(TCGContext *s)
                 uint32_t b = temps[args[3]].val;
                 uint64_t r = (uint64_t)a * b;
                 TCGArg rl, rh;
-                TCGOp *op2;
+                TCGOp *op2 = insert_op_before(s, op, INDEX_op_movi_i32, 2);
-                TCGArg *args2;
+                TCGArg *args2 = &s->gen_opparam_buf[op2->args];
-
-                /* We emit the extra nop when we emit the mulu2.  */
-                op2 = &s->gen_op_buf[oi_next];
-                assert(op2->opc == INDEX_op_nop);
-
-                /* But we still have to allocate args for the op.  */
-                op2->args = s->gen_next_parm_idx;
-                s->gen_next_parm_idx += 2;
-                args2 = &s->gen_opparam_buf[op2->args];
 
                 rl = args[0];
                 rh = args[1];

qemu/tcg/tcg-op.c

@@ -58,11 +58,6 @@ static void tcg_emit_op(TCGContext *ctx, TCGOpcode opc, int args)
     ctx->gen_op_buf[oi] = op;
 }
 
-void tcg_gen_op0(TCGContext *ctx, TCGOpcode opc)
-{
-    tcg_emit_op(ctx, opc, -1);
-}
-
 void tcg_gen_op1(TCGContext *ctx, TCGOpcode opc, TCGArg a1)
 {
     int pi = ctx->gen_next_parm_idx;
@@ -572,8 +567,6 @@ void tcg_gen_add2_i32(TCGContext *s, TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
 {
     if (TCG_TARGET_HAS_add2_i32) {
         tcg_gen_op6_i32(s, INDEX_op_add2_i32, rl, rh, al, ah, bl, bh);
-        /* Allow the optimizer room to replace add2 with two moves.  */
-        tcg_gen_op0(s, INDEX_op_nop);
     } else {
         TCGv_i64 t0 = tcg_temp_new_i64(s);
         TCGv_i64 t1 = tcg_temp_new_i64(s);
@@ -591,8 +584,6 @@ void tcg_gen_sub2_i32(TCGContext *s, TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
 {
     if (TCG_TARGET_HAS_sub2_i32) {
         tcg_gen_op6_i32(s, INDEX_op_sub2_i32, rl, rh, al, ah, bl, bh);
-        /* Allow the optimizer room to replace sub2 with two moves.  */
-        tcg_gen_op0(s, INDEX_op_nop);
     } else {
         TCGv_i64 t0 = tcg_temp_new_i64(s);
         TCGv_i64 t1 = tcg_temp_new_i64(s);
@@ -609,8 +600,6 @@ void tcg_gen_mulu2_i32(TCGContext *s, TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, T
 {
     if (TCG_TARGET_HAS_mulu2_i32) {
         tcg_gen_op4_i32(s, INDEX_op_mulu2_i32, rl, rh, arg1, arg2);
-        /* Allow the optimizer room to replace mulu2 with two moves.  */
-        tcg_gen_op0(s, INDEX_op_nop);
     } else if (TCG_TARGET_HAS_muluh_i32) {
         TCGv_i32 t = tcg_temp_new_i32(s);
         tcg_gen_op3_i32(s, INDEX_op_mul_i32, t, arg1, arg2);
@@ -633,8 +622,6 @@ void tcg_gen_muls2_i32(TCGContext *s, TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, T
 {
     if (TCG_TARGET_HAS_muls2_i32) {
         tcg_gen_op4_i32(s, INDEX_op_muls2_i32, rl, rh, arg1, arg2);
-        /* Allow the optimizer room to replace muls2 with two moves.  */
-        tcg_gen_op0(s, INDEX_op_nop);
     } else if (TCG_TARGET_HAS_mulsh_i32) {
         TCGv_i32 t = tcg_temp_new_i32(s);
         tcg_gen_op3_i32(s, INDEX_op_mul_i32, t, arg1, arg2);
@@ -1649,8 +1636,6 @@ void tcg_gen_add2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
 {
     if (TCG_TARGET_HAS_add2_i64) {
         tcg_gen_op6_i64(s, INDEX_op_add2_i64, rl, rh, al, ah, bl, bh);
-        /* Allow the optimizer room to replace add2 with two moves.  */
-        tcg_gen_op0(s, INDEX_op_nop);
     } else {
         TCGv_i64 t0 = tcg_temp_new_i64(s);
         TCGv_i64 t1 = tcg_temp_new_i64(s);
@@ -1669,8 +1654,6 @@ void tcg_gen_sub2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
 {
     if (TCG_TARGET_HAS_sub2_i64) {
         tcg_gen_op6_i64(s, INDEX_op_sub2_i64, rl, rh, al, ah, bl, bh);
-        /* Allow the optimizer room to replace sub2 with two moves.  */
-        tcg_gen_op0(s, INDEX_op_nop);
     } else {
         TCGv_i64 t0 = tcg_temp_new_i64(s);
         TCGv_i64 t1 = tcg_temp_new_i64(s);
@@ -1688,8 +1671,6 @@ void tcg_gen_mulu2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, T
 {
     if (TCG_TARGET_HAS_mulu2_i64) {
         tcg_gen_op4_i64(s, INDEX_op_mulu2_i64, rl, rh, arg1, arg2);
-        /* Allow the optimizer room to replace mulu2 with two moves.  */
-        tcg_gen_op0(s, INDEX_op_nop);
     } else if (TCG_TARGET_HAS_muluh_i64) {
         TCGv_i64 t = tcg_temp_new_i64(s);
         tcg_gen_op3_i64(s, INDEX_op_mul_i64, t, arg1, arg2);
@@ -1709,8 +1690,6 @@ void tcg_gen_muls2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, T
 {
     if (TCG_TARGET_HAS_muls2_i64) {
         tcg_gen_op4_i64(s, INDEX_op_muls2_i64, rl, rh, arg1, arg2);
-        /* Allow the optimizer room to replace muls2 with two moves.  */
-        tcg_gen_op0(s, INDEX_op_nop);
     } else if (TCG_TARGET_HAS_mulsh_i64) {
         TCGv_i64 t = tcg_temp_new_i64(s);
         tcg_gen_op3_i64(s, INDEX_op_mul_i64, t, arg1, arg2);

qemu/tcg/tcg-op.h

@@ -27,7 +27,6 @@
 #include "exec/helper-gen.h"
 
 /* Basic output routines.  Not for general consumption.  */
-void tcg_gen_op0(TCGContext *, TCGOpcode);
 void tcg_gen_op1(TCGContext *, TCGOpcode, TCGArg);
 void tcg_gen_op2(TCGContext *, TCGOpcode, TCGArg, TCGArg);
 void tcg_gen_op3(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg);

qemu/x86_64.h

@@ -2774,7 +2774,6 @@
 #define tcg_gen_nor_i64 tcg_gen_nor_i64_x86_64
 #define tcg_gen_not_i32 tcg_gen_not_i32_x86_64
 #define tcg_gen_not_i64 tcg_gen_not_i64_x86_64
-#define tcg_gen_op0 tcg_gen_op0_x86_64
 #define tcg_gen_op1 tcg_gen_op1_x86_64
 #define tcg_gen_op2 tcg_gen_op2_x86_64
 #define tcg_gen_op3 tcg_gen_op3_x86_64