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https://github.com/yuzu-emu/unicorn.git
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tcg/mips: Fully convert tcg_target_op_def
Backports commit 89b2e37e6506d92b00ac478e7953be6ddd7a86a9 from qemu
This commit is contained in:
Richard Henderson
Lioncash
parent
24c5be0472
commit
7168f72d4d
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@ -2178,165 +2178,167 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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}
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}
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static const TCGTargetOpDef mips_op_defs[] = {
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{ INDEX_op_exit_tb, { } },
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{ INDEX_op_goto_tb, { } },
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{ INDEX_op_br, { } },
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{ INDEX_op_goto_ptr, { "r" } },
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{ INDEX_op_ld8u_i32, { "r", "r" } },
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{ INDEX_op_ld8s_i32, { "r", "r" } },
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{ INDEX_op_ld16u_i32, { "r", "r" } },
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{ INDEX_op_ld16s_i32, { "r", "r" } },
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{ INDEX_op_ld_i32, { "r", "r" } },
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{ INDEX_op_st8_i32, { "rZ", "r" } },
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{ INDEX_op_st16_i32, { "rZ", "r" } },
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{ INDEX_op_st_i32, { "rZ", "r" } },
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{ INDEX_op_add_i32, { "r", "rZ", "rJ" } },
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{ INDEX_op_mul_i32, { "r", "rZ", "rZ" } },
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#if !use_mips32r6_instructions
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{ INDEX_op_muls2_i32, { "r", "r", "rZ", "rZ" } },
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{ INDEX_op_mulu2_i32, { "r", "r", "rZ", "rZ" } },
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#endif
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{ INDEX_op_mulsh_i32, { "r", "rZ", "rZ" } },
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{ INDEX_op_muluh_i32, { "r", "rZ", "rZ" } },
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{ INDEX_op_div_i32, { "r", "rZ", "rZ" } },
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{ INDEX_op_divu_i32, { "r", "rZ", "rZ" } },
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{ INDEX_op_rem_i32, { "r", "rZ", "rZ" } },
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{ INDEX_op_remu_i32, { "r", "rZ", "rZ" } },
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{ INDEX_op_sub_i32, { "r", "rZ", "rN" } },
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{ INDEX_op_and_i32, { "r", "rZ", "rIK" } },
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{ INDEX_op_nor_i32, { "r", "rZ", "rZ" } },
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{ INDEX_op_not_i32, { "r", "rZ" } },
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{ INDEX_op_or_i32, { "r", "rZ", "rIZ" } },
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{ INDEX_op_xor_i32, { "r", "rZ", "rIZ" } },
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{ INDEX_op_shl_i32, { "r", "rZ", "ri" } },
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{ INDEX_op_shr_i32, { "r", "rZ", "ri" } },
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{ INDEX_op_sar_i32, { "r", "rZ", "ri" } },
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{ INDEX_op_rotr_i32, { "r", "rZ", "ri" } },
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{ INDEX_op_rotl_i32, { "r", "rZ", "ri" } },
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{ INDEX_op_clz_i32, { "r", "r", "rWZ" } },
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{ INDEX_op_bswap16_i32, { "r", "r" } },
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{ INDEX_op_bswap32_i32, { "r", "r" } },
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{ INDEX_op_ext8s_i32, { "r", "rZ" } },
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{ INDEX_op_ext16s_i32, { "r", "rZ" } },
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{ INDEX_op_deposit_i32, { "r", "0", "rZ" } },
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{ INDEX_op_extract_i32, { "r", "r" } },
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{ INDEX_op_brcond_i32, { "rZ", "rZ" } },
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#if use_mips32r6_instructions
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{ INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rZ", "rZ" } },
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#else
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{ INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rZ", "0" } },
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#endif
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{ INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
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#if TCG_TARGET_REG_BITS == 32
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{ INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rN", "rN" } },
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{ INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rN", "rN" } },
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{ INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rZ", "rZ" } },
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{ INDEX_op_brcond2_i32, { "rZ", "rZ", "rZ", "rZ" } },
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#endif
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#if TCG_TARGET_REG_BITS == 64
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{ INDEX_op_ld8u_i64, { "r", "r" } },
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{ INDEX_op_ld8s_i64, { "r", "r" } },
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{ INDEX_op_ld16u_i64, { "r", "r" } },
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{ INDEX_op_ld16s_i64, { "r", "r" } },
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{ INDEX_op_ld32s_i64, { "r", "r" } },
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{ INDEX_op_ld32u_i64, { "r", "r" } },
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{ INDEX_op_ld_i64, { "r", "r" } },
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{ INDEX_op_st8_i64, { "rZ", "r" } },
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{ INDEX_op_st16_i64, { "rZ", "r" } },
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{ INDEX_op_st32_i64, { "rZ", "r" } },
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{ INDEX_op_st_i64, { "rZ", "r" } },
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{ INDEX_op_add_i64, { "r", "rZ", "rJ" } },
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{ INDEX_op_mul_i64, { "r", "rZ", "rZ" } },
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#if !use_mips32r6_instructions
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{ INDEX_op_muls2_i64, { "r", "r", "rZ", "rZ" } },
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{ INDEX_op_mulu2_i64, { "r", "r", "rZ", "rZ" } },
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#endif
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{ INDEX_op_mulsh_i64, { "r", "rZ", "rZ" } },
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{ INDEX_op_muluh_i64, { "r", "rZ", "rZ" } },
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{ INDEX_op_div_i64, { "r", "rZ", "rZ" } },
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{ INDEX_op_divu_i64, { "r", "rZ", "rZ" } },
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{ INDEX_op_rem_i64, { "r", "rZ", "rZ" } },
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{ INDEX_op_remu_i64, { "r", "rZ", "rZ" } },
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{ INDEX_op_sub_i64, { "r", "rZ", "rN" } },
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{ INDEX_op_and_i64, { "r", "rZ", "rIK" } },
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{ INDEX_op_nor_i64, { "r", "rZ", "rZ" } },
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{ INDEX_op_not_i64, { "r", "rZ" } },
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{ INDEX_op_or_i64, { "r", "rZ", "rI" } },
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{ INDEX_op_xor_i64, { "r", "rZ", "rI" } },
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{ INDEX_op_shl_i64, { "r", "rZ", "ri" } },
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{ INDEX_op_shr_i64, { "r", "rZ", "ri" } },
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{ INDEX_op_sar_i64, { "r", "rZ", "ri" } },
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{ INDEX_op_rotr_i64, { "r", "rZ", "ri" } },
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{ INDEX_op_rotl_i64, { "r", "rZ", "ri" } },
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{ INDEX_op_clz_i64, { "r", "r", "rWZ" } },
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{ INDEX_op_bswap16_i64, { "r", "r" } },
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{ INDEX_op_bswap32_i64, { "r", "r" } },
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{ INDEX_op_bswap64_i64, { "r", "r" } },
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{ INDEX_op_ext8s_i64, { "r", "rZ" } },
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{ INDEX_op_ext16s_i64, { "r", "rZ" } },
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{ INDEX_op_ext32s_i64, { "r", "rZ" } },
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{ INDEX_op_ext32u_i64, { "r", "rZ" } },
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{ INDEX_op_ext_i32_i64, { "r", "rZ" } },
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{ INDEX_op_extu_i32_i64, { "r", "rZ" } },
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{ INDEX_op_extrl_i64_i32, { "r", "rZ" } },
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{ INDEX_op_extrh_i64_i32, { "r", "rZ" } },
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{ INDEX_op_deposit_i64, { "r", "0", "rZ" } },
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{ INDEX_op_extract_i64, { "r", "r" } },
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{ INDEX_op_brcond_i64, { "rZ", "rZ" } },
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#if use_mips32r6_instructions
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{ INDEX_op_movcond_i64, { "r", "rZ", "rZ", "rZ", "rZ" } },
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#else
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{ INDEX_op_movcond_i64, { "r", "rZ", "rZ", "rZ", "0" } },
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#endif
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{ INDEX_op_setcond_i64, { "r", "rZ", "rZ" } },
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{ INDEX_op_qemu_ld_i32, { "r", "LZ" } },
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{ INDEX_op_qemu_st_i32, { "SZ", "SZ" } },
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{ INDEX_op_qemu_ld_i64, { "r", "LZ" } },
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{ INDEX_op_qemu_st_i64, { "SZ", "SZ" } },
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#elif TARGET_LONG_BITS == 32
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{ INDEX_op_qemu_ld_i32, { "r", "LZ" } },
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{ INDEX_op_qemu_st_i32, { "SZ", "SZ" } },
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{ INDEX_op_qemu_ld_i64, { "r", "r", "LZ" } },
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{ INDEX_op_qemu_st_i64, { "SZ", "SZ", "SZ" } },
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#else
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{ INDEX_op_qemu_ld_i32, { "r", "LZ", "LZ" } },
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{ INDEX_op_qemu_st_i32, { "SZ", "SZ", "SZ" } },
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{ INDEX_op_qemu_ld_i64, { "r", "r", "LZ", "LZ" } },
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{ INDEX_op_qemu_st_i64, { "SZ", "SZ", "SZ", "SZ" } },
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#endif
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{ INDEX_op_mb, { } },
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{ -1 },
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};
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static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
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{
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int i, n = ARRAY_SIZE(mips_op_defs);
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static const TCGTargetOpDef r = { 0, { "r" } };
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static const TCGTargetOpDef r_r = { 0, { "r", "r" } };
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static const TCGTargetOpDef r_L = { 0, { "r", "L" } };
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static const TCGTargetOpDef rZ_r = { 0, { "rZ", "r" } };
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static const TCGTargetOpDef SZ_S = { 0, { "SZ", "S" } };
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static const TCGTargetOpDef rZ_rZ = { 0, { "rZ", "rZ" } };
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static const TCGTargetOpDef r_r_L = { 0, { "r", "r", "L" } };
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static const TCGTargetOpDef r_L_L = { 0, { "r", "L", "L" } };
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static const TCGTargetOpDef r_r_ri = { 0, { "r", "r", "ri" } };
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static const TCGTargetOpDef r_r_rI = { 0, { "r", "r", "rI" } };
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static const TCGTargetOpDef r_r_rJ = { 0, { "r", "r", "rJ" } };
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static const TCGTargetOpDef SZ_S_S = { 0, { "SZ", "S", "S" } };
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static const TCGTargetOpDef SZ_SZ_S = { 0, { "SZ", "SZ", "S" } };
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static const TCGTargetOpDef SZ_SZ_S_S = { 0, { "SZ", "SZ", "S", "S" } };
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static const TCGTargetOpDef r_rZ_rN = { 0, { "r", "rZ", "rN" } };
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static const TCGTargetOpDef r_rZ_rZ = { 0, { "r", "rZ", "rZ" } };
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static const TCGTargetOpDef r_r_rIK = { 0, { "r", "r", "rIK" } };
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static const TCGTargetOpDef r_r_rWZ = { 0, { "r", "r", "rWZ" } };
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static const TCGTargetOpDef r_r_r_r = { 0, { "r", "r", "r", "r" } };
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static const TCGTargetOpDef r_r_L_L = { 0, { "r", "r", "L", "L" } };
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static const TCGTargetOpDef dep = { 0, { "r", "0", "rZ" } };
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static const TCGTargetOpDef movc = { 0, { "r", "rZ", "rZ", "rZ", "0" } };
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static const TCGTargetOpDef movc_r6 = { 0, { "r", "rZ", "rZ", "rZ", "rZ" } };
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static const TCGTargetOpDef add2 = { 0, { "r", "r", "rZ", "rZ", "rN", "rN" } };
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static const TCGTargetOpDef br2 = { 0, { "rZ", "rZ", "rZ", "rZ" } };
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static const TCGTargetOpDef setc2 = { 0, { "r", "rZ", "rZ", "rZ", "rZ" } };
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for (i = 0; i < n; ++i) {
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if (mips_op_defs[i].op == op) {
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return &mips_op_defs[i];
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}
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}
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switch (op) {
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case INDEX_op_goto_ptr:
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return &r;
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case INDEX_op_ld8u_i32:
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case INDEX_op_ld8s_i32:
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case INDEX_op_ld16u_i32:
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case INDEX_op_ld16s_i32:
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case INDEX_op_ld_i32:
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case INDEX_op_not_i32:
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case INDEX_op_bswap16_i32:
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case INDEX_op_bswap32_i32:
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case INDEX_op_ext8s_i32:
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case INDEX_op_ext16s_i32:
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case INDEX_op_extract_i32:
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case INDEX_op_ld8u_i64:
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case INDEX_op_ld8s_i64:
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case INDEX_op_ld16u_i64:
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case INDEX_op_ld16s_i64:
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case INDEX_op_ld32s_i64:
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case INDEX_op_ld32u_i64:
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case INDEX_op_ld_i64:
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case INDEX_op_not_i64:
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case INDEX_op_bswap16_i64:
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case INDEX_op_bswap32_i64:
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case INDEX_op_bswap64_i64:
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case INDEX_op_ext8s_i64:
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case INDEX_op_ext16s_i64:
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case INDEX_op_ext32s_i64:
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case INDEX_op_ext32u_i64:
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case INDEX_op_ext_i32_i64:
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case INDEX_op_extu_i32_i64:
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case INDEX_op_extrl_i64_i32:
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case INDEX_op_extrh_i64_i32:
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case INDEX_op_extract_i64:
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return &r_r;
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case INDEX_op_st8_i32:
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case INDEX_op_st16_i32:
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case INDEX_op_st_i32:
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case INDEX_op_st8_i64:
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case INDEX_op_st16_i64:
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case INDEX_op_st32_i64:
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case INDEX_op_st_i64:
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return &rZ_r;
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case INDEX_op_add_i32:
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case INDEX_op_add_i64:
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return &r_r_rJ;
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case INDEX_op_sub_i32:
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case INDEX_op_sub_i64:
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return &r_rZ_rN;
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case INDEX_op_mul_i32:
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case INDEX_op_mulsh_i32:
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case INDEX_op_muluh_i32:
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case INDEX_op_div_i32:
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case INDEX_op_divu_i32:
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case INDEX_op_rem_i32:
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case INDEX_op_remu_i32:
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case INDEX_op_nor_i32:
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case INDEX_op_setcond_i32:
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case INDEX_op_mul_i64:
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case INDEX_op_mulsh_i64:
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case INDEX_op_muluh_i64:
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case INDEX_op_div_i64:
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case INDEX_op_divu_i64:
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case INDEX_op_rem_i64:
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case INDEX_op_remu_i64:
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case INDEX_op_nor_i64:
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case INDEX_op_setcond_i64:
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return &r_rZ_rZ;
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case INDEX_op_muls2_i32:
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case INDEX_op_mulu2_i32:
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case INDEX_op_muls2_i64:
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case INDEX_op_mulu2_i64:
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return &r_r_r_r;
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case INDEX_op_and_i32:
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case INDEX_op_and_i64:
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return &r_r_rIK;
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case INDEX_op_or_i32:
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case INDEX_op_xor_i32:
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case INDEX_op_or_i64:
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case INDEX_op_xor_i64:
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return &r_r_rI;
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case INDEX_op_shl_i32:
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case INDEX_op_shr_i32:
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case INDEX_op_sar_i32:
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case INDEX_op_rotr_i32:
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case INDEX_op_rotl_i32:
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case INDEX_op_shl_i64:
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case INDEX_op_shr_i64:
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case INDEX_op_sar_i64:
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case INDEX_op_rotr_i64:
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case INDEX_op_rotl_i64:
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return &r_r_ri;
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case INDEX_op_clz_i32:
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case INDEX_op_clz_i64:
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return &r_r_rWZ;
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case INDEX_op_deposit_i32:
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case INDEX_op_deposit_i64:
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return &dep;
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case INDEX_op_brcond_i32:
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case INDEX_op_brcond_i64:
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return &rZ_rZ;
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case INDEX_op_movcond_i32:
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case INDEX_op_movcond_i64:
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return use_mips32r6_instructions ? &movc_r6 : &movc;
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case INDEX_op_add2_i32:
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case INDEX_op_sub2_i32:
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return &add2;
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case INDEX_op_setcond2_i32:
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return &setc2;
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case INDEX_op_brcond2_i32:
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return &br2;
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case INDEX_op_qemu_ld_i32:
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return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
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? &r_L : &r_L_L);
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case INDEX_op_qemu_st_i32:
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return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
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? &SZ_S : &SZ_S_S);
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case INDEX_op_qemu_ld_i64:
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return (TCG_TARGET_REG_BITS == 64 ? &r_L
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: TARGET_LONG_BITS == 32 ? &r_r_L : &r_r_L_L);
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case INDEX_op_qemu_st_i64:
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return (TCG_TARGET_REG_BITS == 64 ? &SZ_S
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: TARGET_LONG_BITS == 32 ? &SZ_SZ_S : &SZ_SZ_S_S);
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default:
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return NULL;
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}
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||||
}
|
||||
|
||||
static int tcg_target_callee_save_regs[] = {
|
||||
|
|
|
|||
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Reference in a new issue