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tcg: Remove TCG_CT_REG

Browse source 
This wasn't actually used for anything, really. All variable
operands must accept registers, and which are indicated by the
set in TCGArgConstraint.regs.

Backports commit 74a117906b87ff9220e4baae5a7431d6f4eadd45
This commit is contained in:
Richard Henderson 2021-03-01 19:37:57 -05:00 committed by Lioncash
parent ae075d324d
commit 71a34d84e5
9 changed files with 4 additions and 45 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
qemu/tcg/aarch64/tcg-target.inc.c
View file

@ -128,15 +128,12 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
{
switch (*ct_str++) {
case 'r': /* general registers */
ct->ct |= TCG_CT_REG;
ct->regs |= 0xffffffffu;
break;
case 'w': /* advsimd registers */
ct->ct |= TCG_CT_REG;
ct->regs |= 0xffffffff00000000ull;
break;
case 'l': /* qemu_ld / qemu_st address, data_reg */
ct->ct |= TCG_CT_REG;
ct->regs = 0xffffffffu;
#ifdef CONFIG_SOFTMMU
/* x0 and x1 will be overwritten when reading the tlb entry,

3
qemu/tcg/arm/tcg-target.inc.c
View file

@ -253,13 +253,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
break;
case 'r':
ct->ct |= TCG_CT_REG;
ct->regs = 0xffff;
break;
/* qemu_ld address */
case 'l':
ct->ct |= TCG_CT_REG;
ct->regs = 0xffff;
#ifdef CONFIG_SOFTMMU
/* r0-r2,lr will be overwritten when reading the tlb entry,
@ -273,7 +271,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
/* qemu_st address & data */
case 's':
ct->ct |= TCG_CT_REG;
ct->regs = 0xffff;
/* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
and r0-r1 doing the byte swapping, so don't use these. */

11
qemu/tcg/i386/tcg-target.inc.c
View file

@ -215,42 +215,33 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
{
switch(*ct_str++) {
case 'a':
ct->ct |= TCG_CT_REG;
tcg_regset_set_reg(ct->regs, TCG_REG_EAX);
break;
case 'b':
ct->ct |= TCG_CT_REG;
tcg_regset_set_reg(ct->regs, TCG_REG_EBX);
break;
case 'c':
ct->ct |= TCG_CT_REG;
tcg_regset_set_reg(ct->regs, TCG_REG_ECX);
break;
case 'd':
ct->ct |= TCG_CT_REG;
tcg_regset_set_reg(ct->regs, TCG_REG_EDX);
break;
case 'S':
ct->ct |= TCG_CT_REG;
tcg_regset_set_reg(ct->regs, TCG_REG_ESI);
break;
case 'D':
ct->ct |= TCG_CT_REG;
tcg_regset_set_reg(ct->regs, TCG_REG_EDI);
break;
case 'q':
/* A register that can be used as a byte operand. */
ct->ct |= TCG_CT_REG;
ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
break;
case 'Q':
/* A register with an addressable second byte (e.g. %ah). */
ct->ct |= TCG_CT_REG;
ct->regs = 0xf;
break;
case 'r':
/* A general register. */
ct->ct |= TCG_CT_REG;
ct->regs |= ALL_GENERAL_REGS;
break;
case 'W':
@ -259,13 +250,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
break;
case 'x':
/* A vector register. */
ct->ct |= TCG_CT_REG;
ct->regs |= ALL_VECTOR_REGS;
break;
/* qemu_ld/st address constraint */
case 'L':
ct->ct |= TCG_CT_REG;
ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
tcg_regset_reset_reg(ct->regs, TCG_REG_L1);

3
qemu/tcg/mips/tcg-target.inc.c
View file

@ -195,11 +195,9 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
{
switch(*ct_str++) {
case 'r':
ct->ct |= TCG_CT_REG;
ct->regs = 0xffffffff;
break;
case 'L': /* qemu_ld input arg constraint */
ct->ct |= TCG_CT_REG;
ct->regs = 0xffffffff;
tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
#if defined(CONFIG_SOFTMMU)
@ -209,7 +207,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
#endif
break;
case 'S': /* qemu_st constraint */
ct->ct |= TCG_CT_REG;
ct->regs = 0xffffffff;
tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
#if defined(CONFIG_SOFTMMU)

4
qemu/tcg/ppc/tcg-target.inc.c
View file

@ -226,15 +226,12 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
{
switch (*ct_str++) {
case 'A': case 'B': case 'C': case 'D':
ct->ct |= TCG_CT_REG;
tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A');
break;
case 'r':
ct->ct |= TCG_CT_REG;
ct->regs = 0xffffffff;
break;
case 'L': /* qemu_ld constraint */
ct->ct |= TCG_CT_REG;
ct->regs = 0xffffffff;
tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
#ifdef CONFIG_SOFTMMU
@ -243,7 +240,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
#endif
break;
case 'S': /* qemu_st constraint */
ct->ct |= TCG_CT_REG;
ct->regs = 0xffffffff;
tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
#ifdef CONFIG_SOFTMMU

4
qemu/tcg/s390/tcg-target.inc.c
View file

@ -414,23 +414,19 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
{
switch (*ct_str++) {
case 'r': /* all registers */
ct->ct |= TCG_CT_REG;
ct->regs = 0xffff;
break;
case 'L': /* qemu_ld/st constraint */
ct->ct |= TCG_CT_REG;
ct->regs = 0xffff;
tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
break;
case 'a': /* force R2 for division */
ct->ct |= TCG_CT_REG;
ct->regs = 0;
tcg_regset_set_reg(ct->regs, TCG_REG_R2);
break;
case 'b': /* force R3 for division */
ct->ct |= TCG_CT_REG;
ct->regs = 0;
tcg_regset_set_reg(ct->regs, TCG_REG_R3);
break;

5
qemu/tcg/sparc/tcg-target.inc.c
View file

@ -328,15 +328,12 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
{
switch (*ct_str++) {
case 'r':
ct->ct |= TCG_CT_REG;
ct->regs = 0xffffffff;
break;
case 'R':
ct->ct |= TCG_CT_REG;
ct->regs = ALL_64;
break;
case 'A': /* qemu_ld/st address constraint */
ct->ct |= TCG_CT_REG;
ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
reserve_helpers:
tcg_regset_reset_reg(ct->regs, TCG_REG_O0);
@ -344,11 +341,9 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
tcg_regset_reset_reg(ct->regs, TCG_REG_O2);
break;
case 's': /* qemu_st data 32-bit constraint */
ct->ct |= TCG_CT_REG;
ct->regs = 0xffffffff;
goto reserve_helpers;
case 'S': /* qemu_st data 64-bit constraint */
ct->ct |= TCG_CT_REG;
ct->regs = ALL_64;
goto reserve_helpers;
case 'I':

15
qemu/tcg/tcg.c
View file

@ -1587,21 +1587,14 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs)
/* we give more priority to constraints with less registers */
static int get_constraint_priority(const TCGOpDef *def, int k)
{
const TCGArgConstraint *arg_ct;
const TCGArgConstraint *arg_ct = &def->args_ct[k];
int n;
int i, n;
arg_ct = &def->args_ct[k];
if (arg_ct->ct & TCG_CT_ALIAS) {
/* an alias is equivalent to a single register */
n = 1;
} else {
if (!(arg_ct->ct & TCG_CT_REG))
return 0;
n = 0;
for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
if (tcg_regset_test_reg(arg_ct->regs, i))
n++;
}
n = ctpop64(arg_ct->regs);
}
return TCG_TARGET_NB_REGS - n + 1;
}
@ -1678,7 +1671,7 @@ static void process_op_defs(TCGContext *s)
int oarg = *ct_str - '0';
tcg_debug_assert(ct_str == tdefs->args_ct_str[i]);
tcg_debug_assert(oarg < def->nb_oargs);
tcg_debug_assert(def->args_ct[oarg].ct & TCG_CT_REG);
tcg_debug_assert(def->args_ct[oarg].regs != 0);
/* TCG_CT_ALIAS is for the output arguments.
The input is tagged with TCG_CT_IALIAS. */
def->args_ct[i] = def->args_ct[oarg];

1
qemu/tcg/tcg.h
View file

@ -621,7 +621,6 @@ void tcg_dump_info(void);
#define TCG_CT_ALIAS 0x80
#define TCG_CT_IALIAS 0x40
#define TCG_CT_NEWREG 0x20 /* output requires a new register */
#define TCG_CT_REG 0x01
#define TCG_CT_CONST 0x02 /* any constant of register size */
typedef struct TCGArgConstraint {