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target/arm: Enable ARMv8.2-ATS1E1 in -cpu max

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This includes enablement of ARMv8.1-PAN.

Backports commit e0fe7309a7c21ef2386de50d37c86aea0d671c08 from qemu
This commit is contained in:
Richard Henderson 2020-03-21 17:43:52 -04:00 committed by Lioncash
parent d196288b4f
commit 7287bf16b8
2 changed files with 9 additions and 0 deletions
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4
qemu/target/arm/cpu.c
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@ -1925,6 +1925,10 @@ static void arm_max_initfn(struct uc_struct *uc, Object *obj, void *opaque)
t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
cpu->isar.mvfr2 = t;
t = cpu->id_mmfr3;
t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
cpu->id_mmfr3 = t;
t = cpu->id_mmfr4;
t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
cpu->id_mmfr4 = t;

5
qemu/target/arm/cpu64.c
View file

@ -317,6 +317,7 @@ static void aarch64_max_initfn(struct uc_struct *uc, Object *obj, void *opaque)
t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
cpu->isar.id_aa64mmfr1 = t;
/* Replicate the same data to the 32-bit id registers. */
@ -337,6 +338,10 @@ static void aarch64_max_initfn(struct uc_struct *uc, Object *obj, void *opaque)
u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
cpu->isar.id_isar6 = u;
u = cpu->id_mmfr3;
u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
cpu->id_mmfr3 = u;
// Unicorn: we lie and enable them anyway
/*
* FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet,