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target-arm: Implement MDCR_EL2.TDRA traps

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Implement trapping of the "debug ROM" registers, which are controlled
by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.

Backports commit 91b0a23865558e2ce9c2e7042d404e8bf2e4b817 from qemu
This commit is contained in:
Peter Maydell 2018-02-20 14:54:51 -05:00 committed by Lioncash
parent 537ff96e34
commit 7295676caf
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 24 additions and 3 deletions
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27
qemu/target-arm/helper.c
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@ -310,6 +310,24 @@ static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri,
return CP_ACCESS_OK;
}
/* Check for traps to "debug ROM" registers, which are controlled
* by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
*/
static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
int el = arm_current_el(env);
if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDRA)
&& !arm_is_secure_below_el3(env)) {
return CP_ACCESS_TRAP_EL2;
}
if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
return CP_ACCESS_TRAP_EL3;
}
return CP_ACCESS_OK;
}
static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
ARMCPU *cpu = arm_env_get_cpu(env);
@ -3265,11 +3283,14 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
* accessor.
*/
{ "DBGDRAR", 14,1,0, 0,0,0, 0,
ARM_CP_CONST, PL0_R, 0, NULL, 0 },
ARM_CP_CONST, PL0_R, 0, NULL, 0, 0, {0, 0},
access_tdra },
{ "MDRAR_EL1", 0,1,0, 2,0,0, ARM_CP_STATE_AA64,
ARM_CP_CONST, PL1_R, 0, NULL, 0 },
ARM_CP_CONST, PL1_R, 0, NULL, 0, 0, {0, 0},
access_tdra },
{ "DBGDSAR", 14,2,0, 0,0,0, 0,
ARM_CP_CONST, PL0_R, 0, NULL, 0 },
ARM_CP_CONST, PL0_R, 0, NULL, 0, 0, {0, 0},
access_tdra },
/* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
{ "MDSCR_EL1", 14,0,2, 2,0,2, ARM_CP_STATE_BOTH,
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mdscr_el1), },