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i386: Update stepping of Cascadelake-Server

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Update the stepping from 5 to 6, in order that
the Cascadelake-Server CPU model can support AVX512VNNI
and MSR based features exposed by ARCH_CAPABILITIES.

Backports commit b0a1980384fc265d91de7e09aa5fe531a69e6288 from qemu
This commit is contained in:
Tao Xu 2019-02-03 17:11:15 -05:00 committed by Lioncash
parent b36f8220b2
commit 72afbf6d48
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 1 additions and 1 deletions
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qemu/target/i386/cpu.c
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@ -3064,7 +3064,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.vendor = CPUID_VENDOR_INTEL, .vendor = CPUID_VENDOR_INTEL,
.family = 6, .family = 6,
.model = 85, .model = 85,
.stepping = 5, .stepping = 6,
.features[FEAT_1_EDX] = .features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |