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target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimd

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Backports 2e5a265e6a9e7169c4a3e87db261b2fa92582590
This commit is contained in:
Richard Henderson 2021-02-26 14:46:21 -05:00 committed by Lioncash
parent 80325ac866
commit 732674b868
6 changed files with 50 additions and 0 deletions
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3
qemu/aarch64.h
View file

@ -3582,6 +3582,9 @@
#define helper_frecpx_f32 helper_frecpx_f32_aarch64
#define helper_frecpx_f64 helper_frecpx_f64_aarch64
#define helper_fjcvtzs helper_fjcvtzs_aarch64
#define helper_gvec_mul_idx_d helper_gvec_mul_idx_d_aarch64
#define helper_gvec_mul_idx_h helper_gvec_mul_idx_h_aarch64
#define helper_gvec_mul_idx_s helper_gvec_mul_idx_s_aarch64
#define helper_gvec_recps_d helper_gvec_recps_d_aarch64
#define helper_gvec_recps_h helper_gvec_recps_h_aarch64
#define helper_gvec_recps_s helper_gvec_recps_s_aarch64

3
qemu/aarch64eb.h
View file

@ -3582,6 +3582,9 @@
#define helper_frecpx_f32 helper_frecpx_f32_aarch64eb
#define helper_frecpx_f64 helper_frecpx_f64_aarch64eb
#define helper_fjcvtzs helper_fjcvtzs_aarch64eb
#define helper_gvec_mul_idx_d helper_gvec_mul_idx_d_aarch64eb
#define helper_gvec_mul_idx_h helper_gvec_mul_idx_h_aarch64eb
#define helper_gvec_mul_idx_s helper_gvec_mul_idx_s_aarch64eb
#define helper_gvec_recps_d helper_gvec_recps_d_aarch64eb
#define helper_gvec_recps_h helper_gvec_recps_h_aarch64eb
#define helper_gvec_recps_s helper_gvec_recps_s_aarch64eb

3
qemu/header_gen.py
View file

@ -3722,6 +3722,9 @@ aarch64_symbols = (
'helper_frecpx_f32',
'helper_frecpx_f64',
'helper_fjcvtzs',
'helper_gvec_mul_idx_d',
'helper_gvec_mul_idx_h',
'helper_gvec_mul_idx_s',
'helper_gvec_recps_d',
'helper_gvec_recps_h',
'helper_gvec_recps_s',

4
qemu/target/arm/helper.h
View file

@ -756,6 +756,10 @@ DEF_HELPER_FLAGS_4(gvec_uaba_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_uaba_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_uaba_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_mul_idx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_mul_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_mul_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
#ifdef TARGET_ARM
#define helper_clz helper_clz_arm
#define gen_helper_clz gen_helper_clz_arm

16
qemu/target/arm/translate-a64.c
View file

@ -13798,6 +13798,22 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
data, gen_helper_gvec_fmlal_idx_a64);
}
return;
case 0x08: /* MUL */
if (!is_long && !is_scalar) {
static gen_helper_gvec_3 * const fns[3] = {
gen_helper_gvec_mul_idx_h,
gen_helper_gvec_mul_idx_s,
gen_helper_gvec_mul_idx_d,
};
tcg_gen_gvec_3_ool(tcg_ctx, vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn),
vec_full_reg_offset(s, rm),
is_q ? 16 : 8, vec_full_reg_size(s),
index, fns[size - 1]);
return;
}
break;
}
if (size == 3) {

21
qemu/target/arm/vec_helper.c
View file

@ -711,6 +711,27 @@ DO_3OP(gvec_rsqrts_d, helper_rsqrtsf_f64, float64)
* For AdvSIMD, there is of course only one such vector segment.
*/
#define DO_MUL_IDX(NAME, TYPE, H) \
void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \
{ \
intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \
intptr_t idx = simd_data(desc); \
TYPE *d = vd, *n = vn, *m = vm; \
for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \
TYPE mm = m[H(i + idx)]; \
for (j = 0; j < segment; j++) { \
d[i + j] = n[i + j] * mm; \
} \
} \
clear_tail(d, oprsz, simd_maxsz(desc)); \
}
DO_MUL_IDX(gvec_mul_idx_h, uint16_t, H2)
DO_MUL_IDX(gvec_mul_idx_s, uint32_t, H4)
DO_MUL_IDX(gvec_mul_idx_d, uint64_t, )
#undef DO_MUL_IDX
#define DO_MUL_IDX(NAME, TYPE, H) \
void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
{ \