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target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interrupt

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The hstatus.GVA bit was not set if the faulting guest virtual address
was zero.

Backports 4aeb9e26c219a85f465eb2cc7ef6939a3c71944f
This commit is contained in:
Georg Kotheimer 2021-03-08 14:39:29 -05:00 committed by Lioncash
parent 640a26bf58
commit 7351f09919
1 changed files with 3 additions and 1 deletions
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4
qemu/target/riscv/cpu_helper.c
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@ -840,6 +840,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
target_ulong deleg = async ? env->mideleg : env->medeleg;
bool write_tval = false;
target_ulong tval = 0;
target_ulong htval = 0;
target_ulong mtval2 = 0;
@ -861,6 +862,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
case RISCV_EXCP_INST_PAGE_FAULT:
case RISCV_EXCP_LOAD_PAGE_FAULT:
case RISCV_EXCP_STORE_PAGE_FAULT:
write_tval = true;
tval = env->badaddr;
break;
default:
@ -897,7 +899,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
if ((riscv_cpu_virt_enabled(env) ||
riscv_cpu_two_stage_lookup(env)) && tval) {
riscv_cpu_two_stage_lookup(env)) && write_tval) {
/*
* If we are writing a guest virtual address to stval, set
* this to 1. If we are trapping to VS we will set this to 0