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target/mips: Add emulation of DSP ASE for nanoMIPS - part 4

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Add emulation of DSP ASE instructions for nanoMIPS - part 4.

Backports commit 8b3698b2947610e0645a65ace4822164d55dd76b from qemu
This commit is contained in:
Stefan Markovic 2018-08-27 06:43:30 -04:00 committed by Lioncash
parent b6602fff1f
commit 73a5efd599
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 365 additions and 0 deletions
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365
qemu/target/mips/translate.c
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@ -17536,6 +17536,367 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
tcg_temp_free(tcg_ctx, v0_t);
}
static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
TCGv v0, TCGv v1, int rd)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv_i32 t0;
t0 = tcg_temp_new_i32(tcg_ctx);
tcg_gen_movi_i32(tcg_ctx, t0, rd >> 3);
switch (opc) {
case NM_POOL32AXF_2_0_7:
switch (extract32(ctx->opcode, 9, 3)) {
case NM_DPA_W_PH:
check_dspr2(ctx);
gen_helper_dpa_w_ph(tcg_ctx, t0, v1, v0, tcg_ctx->cpu_env);
break;
case NM_DPAQ_S_W_PH:
check_dsp(ctx);
gen_helper_dpaq_s_w_ph(tcg_ctx, t0, v1, v0, tcg_ctx->cpu_env);
break;
case NM_DPS_W_PH:
check_dspr2(ctx);
gen_helper_dps_w_ph(tcg_ctx, t0, v1, v0, tcg_ctx->cpu_env);
break;
case NM_DPSQ_S_W_PH:
check_dsp(ctx);
gen_helper_dpsq_s_w_ph(tcg_ctx, t0, v1, v0, tcg_ctx->cpu_env);
break;
default:
generate_exception_end(ctx, EXCP_RI);
break;
}
break;
case NM_POOL32AXF_2_8_15:
switch (extract32(ctx->opcode, 9, 3)) {
case NM_DPAX_W_PH:
check_dspr2(ctx);
gen_helper_dpax_w_ph(tcg_ctx, t0, v0, v1, tcg_ctx->cpu_env);
break;
case NM_DPAQ_SA_L_W:
check_dsp(ctx);
gen_helper_dpaq_sa_l_w(tcg_ctx, t0, v0, v1, tcg_ctx->cpu_env);
break;
case NM_DPSX_W_PH:
check_dspr2(ctx);
gen_helper_dpsx_w_ph(tcg_ctx, t0, v0, v1, tcg_ctx->cpu_env);
break;
case NM_DPSQ_SA_L_W:
check_dsp(ctx);
gen_helper_dpsq_sa_l_w(tcg_ctx, t0, v0, v1, tcg_ctx->cpu_env);
break;
default:
generate_exception_end(ctx, EXCP_RI);
break;
}
break;
case NM_POOL32AXF_2_16_23:
switch (extract32(ctx->opcode, 9, 3)) {
case NM_DPAU_H_QBL:
check_dsp(ctx);
gen_helper_dpau_h_qbl(tcg_ctx, t0, v0, v1, tcg_ctx->cpu_env);
break;
case NM_DPAQX_S_W_PH:
check_dspr2(ctx);
gen_helper_dpaqx_s_w_ph(tcg_ctx, t0, v0, v1, tcg_ctx->cpu_env);
break;
case NM_DPSU_H_QBL:
check_dsp(ctx);
gen_helper_dpsu_h_qbl(tcg_ctx, t0, v0, v1, tcg_ctx->cpu_env);
break;
case NM_DPSQX_S_W_PH:
check_dspr2(ctx);
gen_helper_dpsqx_s_w_ph(tcg_ctx, t0, v0, v1, tcg_ctx->cpu_env);
break;
case NM_MULSA_W_PH:
check_dspr2(ctx);
gen_helper_mulsa_w_ph(tcg_ctx, t0, v0, v1, tcg_ctx->cpu_env);
break;
default:
generate_exception_end(ctx, EXCP_RI);
break;
}
break;
case NM_POOL32AXF_2_24_31:
switch (extract32(ctx->opcode, 9, 3)) {
case NM_DPAU_H_QBR:
check_dsp(ctx);
gen_helper_dpau_h_qbr(tcg_ctx, t0, v1, v0, tcg_ctx->cpu_env);
break;
case NM_DPAQX_SA_W_PH:
check_dspr2(ctx);
gen_helper_dpaqx_sa_w_ph(tcg_ctx, t0, v1, v0, tcg_ctx->cpu_env);
break;
case NM_DPSU_H_QBR:
check_dsp(ctx);
gen_helper_dpsu_h_qbr(tcg_ctx, t0, v1, v0, tcg_ctx->cpu_env);
break;
case NM_DPSQX_SA_W_PH:
check_dspr2(ctx);
gen_helper_dpsqx_sa_w_ph(tcg_ctx, t0, v1, v0, tcg_ctx->cpu_env);
break;
case NM_MULSAQ_S_W_PH:
check_dsp(ctx);
gen_helper_mulsaq_s_w_ph(tcg_ctx, t0, v1, v0, tcg_ctx->cpu_env);
break;
default:
generate_exception_end(ctx, EXCP_RI);
break;
}
break;
default:
generate_exception_end(ctx, EXCP_RI);
break;
}
tcg_temp_free_i32(tcg_ctx, t0);
}
static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
int rt, int rs, int rd)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
int ret = rt;
TCGv t0 = tcg_temp_new(tcg_ctx);
TCGv t1 = tcg_temp_new(tcg_ctx);
TCGv v0_t = tcg_temp_new(tcg_ctx);
TCGv v1_t = tcg_temp_new(tcg_ctx);
gen_load_gpr(ctx, v0_t, rt);
gen_load_gpr(ctx, v1_t, rs);
switch (opc) {
case NM_POOL32AXF_2_0_7:
switch (extract32(ctx->opcode, 9, 3)) {
case NM_DPA_W_PH:
case NM_DPAQ_S_W_PH:
case NM_DPS_W_PH:
case NM_DPSQ_S_W_PH:
gen_pool32axf_2_multiply(ctx, opc, v0_t, v1_t, rd);
break;
case NM_BALIGN:
check_dspr2(ctx);
if (rt != 0) {
gen_load_gpr(ctx, t0, rs);
rd &= 3;
if (rd != 0 && rd != 2) {
tcg_gen_shli_tl(tcg_ctx, tcg_ctx->cpu_gpr[ret], tcg_ctx->cpu_gpr[ret], 8 * rd);
tcg_gen_ext32u_tl(tcg_ctx, t0, t0);
tcg_gen_shri_tl(tcg_ctx, t0, t0, 8 * (4 - rd));
tcg_gen_or_tl(tcg_ctx, tcg_ctx->cpu_gpr[ret], tcg_ctx->cpu_gpr[ret], t0);
}
tcg_gen_ext32s_tl(tcg_ctx, tcg_ctx->cpu_gpr[ret], tcg_ctx->cpu_gpr[ret]);
}
break;
case NM_MADD:
check_dsp(ctx);
{
int acc = extract32(ctx->opcode, 14, 2);
TCGv_i64 t2 = tcg_temp_new_i64(tcg_ctx);
TCGv_i64 t3 = tcg_temp_new_i64(tcg_ctx);
gen_load_gpr(ctx, t0, rt);
gen_load_gpr(ctx, t1, rs);
tcg_gen_ext_tl_i64(tcg_ctx, t2, t0);
tcg_gen_ext_tl_i64(tcg_ctx, t3, t1);
tcg_gen_mul_i64(tcg_ctx, t2, t2, t3);
tcg_gen_concat_tl_i64(tcg_ctx, t3, tcg_ctx->cpu_LO[acc], tcg_ctx->cpu_HI[acc]);
tcg_gen_add_i64(tcg_ctx, t2, t2, t3);
tcg_temp_free_i64(tcg_ctx, t3);
gen_move_low32(tcg_ctx, tcg_ctx->cpu_LO[acc], t2);
gen_move_high32(tcg_ctx, tcg_ctx->cpu_HI[acc], t2);
tcg_temp_free_i64(tcg_ctx, t2);
}
break;
case NM_MULT:
check_dsp(ctx);
{
int acc = extract32(ctx->opcode, 14, 2);
TCGv_i32 t2 = tcg_temp_new_i32(tcg_ctx);
TCGv_i32 t3 = tcg_temp_new_i32(tcg_ctx);
gen_load_gpr(ctx, t0, rs);
gen_load_gpr(ctx, t1, rt);
tcg_gen_trunc_tl_i32(tcg_ctx, t2, t0);
tcg_gen_trunc_tl_i32(tcg_ctx, t3, t1);
tcg_gen_muls2_i32(tcg_ctx, t2, t3, t2, t3);
tcg_gen_ext_i32_tl(tcg_ctx, tcg_ctx->cpu_LO[acc], t2);
tcg_gen_ext_i32_tl(tcg_ctx, tcg_ctx->cpu_HI[acc], t3);
tcg_temp_free_i32(tcg_ctx, t2);
tcg_temp_free_i32(tcg_ctx, t3);
}
break;
case NM_EXTRV_W:
check_dsp(ctx);
gen_load_gpr(ctx, v1_t, rs);
tcg_gen_movi_tl(tcg_ctx, t0, rd >> 3);
gen_helper_extr_w(tcg_ctx, t0, t0, v1_t, tcg_ctx->cpu_env);
gen_store_gpr(tcg_ctx, t0, ret);
break;
}
break;
case NM_POOL32AXF_2_8_15:
switch (extract32(ctx->opcode, 9, 3)) {
case NM_DPAX_W_PH:
case NM_DPAQ_SA_L_W:
case NM_DPSX_W_PH:
case NM_DPSQ_SA_L_W:
gen_pool32axf_2_multiply(ctx, opc, v0_t, v1_t, rd);
break;
case NM_MADDU:
check_dsp(ctx);
{
int acc = extract32(ctx->opcode, 14, 2);
TCGv_i64 t2 = tcg_temp_new_i64(tcg_ctx);
TCGv_i64 t3 = tcg_temp_new_i64(tcg_ctx);
gen_load_gpr(ctx, t0, rs);
gen_load_gpr(ctx, t1, rt);
tcg_gen_ext32u_tl(tcg_ctx, t0, t0);
tcg_gen_ext32u_tl(tcg_ctx, t1, t1);
tcg_gen_extu_tl_i64(tcg_ctx, t2, t0);
tcg_gen_extu_tl_i64(tcg_ctx, t3, t1);
tcg_gen_mul_i64(tcg_ctx, t2, t2, t3);
tcg_gen_concat_tl_i64(tcg_ctx, t3, tcg_ctx->cpu_LO[acc], tcg_ctx->cpu_HI[acc]);
tcg_gen_add_i64(tcg_ctx, t2, t2, t3);
tcg_temp_free_i64(tcg_ctx, t3);
gen_move_low32(tcg_ctx, tcg_ctx->cpu_LO[acc], t2);
gen_move_high32(tcg_ctx, tcg_ctx->cpu_HI[acc], t2);
tcg_temp_free_i64(tcg_ctx, t2);
}
break;
case NM_MULTU:
check_dsp(ctx);
{
int acc = extract32(ctx->opcode, 14, 2);
TCGv_i32 t2 = tcg_temp_new_i32(tcg_ctx);
TCGv_i32 t3 = tcg_temp_new_i32(tcg_ctx);
gen_load_gpr(ctx, t0, rs);
gen_load_gpr(ctx, t1, rt);
tcg_gen_trunc_tl_i32(tcg_ctx, t2, t0);
tcg_gen_trunc_tl_i32(tcg_ctx, t3, t1);
tcg_gen_mulu2_i32(tcg_ctx, t2, t3, t2, t3);
tcg_gen_ext_i32_tl(tcg_ctx, tcg_ctx->cpu_LO[acc], t2);
tcg_gen_ext_i32_tl(tcg_ctx, tcg_ctx->cpu_HI[acc], t3);
tcg_temp_free_i32(tcg_ctx, t2);
tcg_temp_free_i32(tcg_ctx, t3);
}
break;
case NM_EXTRV_R_W:
check_dsp(ctx);
tcg_gen_movi_tl(tcg_ctx, t0, rd >> 3);
gen_helper_extr_r_w(tcg_ctx, t0, t0, v1_t, tcg_ctx->cpu_env);
gen_store_gpr(tcg_ctx, t0, ret);
break;
default:
generate_exception_end(ctx, EXCP_RI);
break;
}
break;
case NM_POOL32AXF_2_16_23:
switch (extract32(ctx->opcode, 9, 3)) {
case NM_DPAU_H_QBL:
case NM_DPAQX_S_W_PH:
case NM_DPSU_H_QBL:
case NM_DPSQX_S_W_PH:
case NM_MULSA_W_PH:
gen_pool32axf_2_multiply(ctx, opc, v0_t, v1_t, rd);
break;
case NM_EXTPV:
check_dsp(ctx);
tcg_gen_movi_tl(tcg_ctx, t0, rd >> 3);
gen_helper_extp(tcg_ctx, t0, t0, v1_t, tcg_ctx->cpu_env);
gen_store_gpr(tcg_ctx, t0, ret);
break;
case NM_MSUB:
check_dsp(ctx);
{
int acc = extract32(ctx->opcode, 14, 2);
TCGv_i64 t2 = tcg_temp_new_i64(tcg_ctx);
TCGv_i64 t3 = tcg_temp_new_i64(tcg_ctx);
gen_load_gpr(ctx, t0, rs);
gen_load_gpr(ctx, t1, rt);
tcg_gen_ext_tl_i64(tcg_ctx, t2, t0);
tcg_gen_ext_tl_i64(tcg_ctx, t3, t1);
tcg_gen_mul_i64(tcg_ctx, t2, t2, t3);
tcg_gen_concat_tl_i64(tcg_ctx, t3, tcg_ctx->cpu_LO[acc], tcg_ctx->cpu_HI[acc]);
tcg_gen_sub_i64(tcg_ctx, t2, t3, t2);
tcg_temp_free_i64(tcg_ctx, t3);
gen_move_low32(tcg_ctx, tcg_ctx->cpu_LO[acc], t2);
gen_move_high32(tcg_ctx, tcg_ctx->cpu_HI[acc], t2);
tcg_temp_free_i64(tcg_ctx, t2);
}
break;
case NM_EXTRV_RS_W:
check_dsp(ctx);
tcg_gen_movi_tl(tcg_ctx, t0, rd >> 3);
gen_helper_extr_rs_w(tcg_ctx, t0, t0, v1_t, tcg_ctx->cpu_env);
gen_store_gpr(tcg_ctx, t0, ret);
break;
}
break;
case NM_POOL32AXF_2_24_31:
switch (extract32(ctx->opcode, 9, 3)) {
case NM_DPAU_H_QBR:
case NM_DPAQX_SA_W_PH:
case NM_DPSU_H_QBR:
case NM_DPSQX_SA_W_PH:
case NM_MULSAQ_S_W_PH:
gen_pool32axf_2_multiply(ctx, opc, v0_t, v1_t, rd);
break;
case NM_EXTPDPV:
check_dsp(ctx);
tcg_gen_movi_tl(tcg_ctx, t0, rd >> 3);
gen_helper_extpdp(tcg_ctx, t0, t0, v1_t, tcg_ctx->cpu_env);
gen_store_gpr(tcg_ctx, t0, ret);
break;
case NM_MSUBU:
check_dsp(ctx);
{
int acc = extract32(ctx->opcode, 14, 2);
TCGv_i64 t2 = tcg_temp_new_i64(tcg_ctx);
TCGv_i64 t3 = tcg_temp_new_i64(tcg_ctx);
gen_load_gpr(ctx, t0, rs);
gen_load_gpr(ctx, t1, rt);
tcg_gen_ext32u_tl(tcg_ctx, t0, t0);
tcg_gen_ext32u_tl(tcg_ctx, t1, t1);
tcg_gen_extu_tl_i64(tcg_ctx, t2, t0);
tcg_gen_extu_tl_i64(tcg_ctx, t3, t1);
tcg_gen_mul_i64(tcg_ctx, t2, t2, t3);
tcg_gen_concat_tl_i64(tcg_ctx, t3, tcg_ctx->cpu_LO[acc], tcg_ctx->cpu_HI[acc]);
tcg_gen_sub_i64(tcg_ctx, t2, t3, t2);
tcg_temp_free_i64(tcg_ctx, t3);
gen_move_low32(tcg_ctx, tcg_ctx->cpu_LO[acc], t2);
gen_move_high32(tcg_ctx, tcg_ctx->cpu_HI[acc], t2);
tcg_temp_free_i64(tcg_ctx, t2);
}
break;
case NM_EXTRV_S_H:
check_dsp(ctx);
tcg_gen_movi_tl(tcg_ctx, t0, rd >> 3);
gen_helper_extr_s_h(tcg_ctx, t0, t0, v0_t, tcg_ctx->cpu_env);
gen_store_gpr(tcg_ctx, t0, ret);
break;
}
break;
default:
generate_exception_end(ctx, EXCP_RI);
break;
}
tcg_temp_free(tcg_ctx, t0);
tcg_temp_free(tcg_ctx, t1);
tcg_temp_free(tcg_ctx, v0_t);
tcg_temp_free(tcg_ctx, v1_t);
}
static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
{
@ -17552,6 +17913,10 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
}
break;
case NM_POOL32AXF_2:
{
int32_t op1 = extract32(ctx->opcode, 12, 2);
gen_pool32axf_2_nanomips_insn(ctx, op1, rt, rs, rd);
}
break;
case NM_POOL32AXF_4:
break;