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target/arm: Fix sign-extension in sve do_ldr/do_str

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The expression (int) imm + (uint32_t) len_align turns into uint32_t
and thus with negative imm produces a memory operation at the wrong
offset. None of the numbers involved are particularly large, so
change everything to use int.

Backports commit 19f2acc915a0f8f443a959844540a6f09133cc96 from qemu
This commit is contained in:
Richard Henderson 2018-08-17 13:48:43 -04:00 committed by Lioncash
parent 1ca7c30fbb
commit 7487c66bee
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 8 additions and 10 deletions
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18
qemu/target/arm/translate-sve.c
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@ -4535,13 +4535,12 @@ static bool trans_UCVTF_dd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
* The load should begin at the address Rn + IMM. * The load should begin at the address Rn + IMM.
*/ */
static void do_ldr(DisasContext *s, uint32_t vofs, uint32_t len, static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
int rn, int imm)
{ {
TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGContext *tcg_ctx = s->uc->tcg_ctx;
uint32_t len_align = QEMU_ALIGN_DOWN(len, 8); int len_align = QEMU_ALIGN_DOWN(len, 8);
uint32_t len_remain = len % 8; int len_remain = len % 8;
uint32_t nparts = len / 8 + ctpop8(len_remain); int nparts = len / 8 + ctpop8(len_remain);
int midx = get_mem_index(s); int midx = get_mem_index(s);
TCGv_i64 addr, t0, t1; TCGv_i64 addr, t0, t1;
@ -4622,12 +4621,11 @@ static void do_ldr(DisasContext *s, uint32_t vofs, uint32_t len,
} }
/* Similarly for stores. */ /* Similarly for stores. */
static void do_str(DisasContext *s, uint32_t vofs, uint32_t len, static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
int rn, int imm)
{ {
uint32_t len_align = QEMU_ALIGN_DOWN(len, 8); int len_align = QEMU_ALIGN_DOWN(len, 8);
uint32_t len_remain = len % 8; int len_remain = len % 8;
uint32_t nparts = len / 8 + ctpop8(len_remain); int nparts = len / 8 + ctpop8(len_remain);
int midx = get_mem_index(s); int midx = get_mem_index(s);
TCGv_i64 addr, t0; TCGv_i64 addr, t0;