mirror of
https://github.com/yuzu-emu/unicorn.git
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target/arm: [tcg] Port to generic translation framework
Backports commit 2316922420da6fd0d1ffb5557d0cdcc5958bcf44 from qemu
This commit is contained in:
parent
cc00feb2df
commit
74d437827b
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@ -1166,8 +1166,6 @@
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#define gen_helper_yield gen_helper_yield_aarch64
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#define gen_helper_yield gen_helper_yield_aarch64
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#define gen_hvc gen_hvc_aarch64
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#define gen_hvc gen_hvc_aarch64
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#define gen_intermediate_code gen_intermediate_code_aarch64
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#define gen_intermediate_code gen_intermediate_code_aarch64
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#define gen_intermediate_code gen_intermediate_code_aarch64
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#define gen_intermediate_code_a64 gen_intermediate_code_a64_aarch64
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#define gen_iwmmxt_address gen_iwmmxt_address_aarch64
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#define gen_iwmmxt_address gen_iwmmxt_address_aarch64
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#define gen_iwmmxt_shift gen_iwmmxt_shift_aarch64
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#define gen_iwmmxt_shift gen_iwmmxt_shift_aarch64
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#define gen_jmp gen_jmp_aarch64
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#define gen_jmp gen_jmp_aarch64
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@ -3437,6 +3435,7 @@
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#define ARM64_REGS_STORAGE_SIZE ARM64_REGS_STORAGE_SIZE_aarch64
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#define ARM64_REGS_STORAGE_SIZE ARM64_REGS_STORAGE_SIZE_aarch64
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#define aarch64_cpu_do_interrupt aarch64_cpu_do_interrupt_aarch64
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#define aarch64_cpu_do_interrupt aarch64_cpu_do_interrupt_aarch64
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#define aarch64_cpu_register_types aarch64_cpu_register_types_aarch64
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#define aarch64_cpu_register_types aarch64_cpu_register_types_aarch64
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#define aarch64_translator_ops aarch64_translator_ops_aarch64
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#define arm64_reg_read arm64_reg_read_aarch64
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#define arm64_reg_read arm64_reg_read_aarch64
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#define arm64_reg_reset arm64_reg_reset_aarch64
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#define arm64_reg_reset arm64_reg_reset_aarch64
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#define arm64_reg_write arm64_reg_write_aarch64
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#define arm64_reg_write arm64_reg_write_aarch64
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@ -1166,8 +1166,6 @@
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#define gen_helper_yield gen_helper_yield_aarch64eb
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#define gen_helper_yield gen_helper_yield_aarch64eb
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#define gen_hvc gen_hvc_aarch64eb
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#define gen_hvc gen_hvc_aarch64eb
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#define gen_intermediate_code gen_intermediate_code_aarch64eb
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#define gen_intermediate_code gen_intermediate_code_aarch64eb
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#define gen_intermediate_code gen_intermediate_code_aarch64eb
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#define gen_intermediate_code_a64 gen_intermediate_code_a64_aarch64eb
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#define gen_iwmmxt_address gen_iwmmxt_address_aarch64eb
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#define gen_iwmmxt_address gen_iwmmxt_address_aarch64eb
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#define gen_iwmmxt_shift gen_iwmmxt_shift_aarch64eb
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#define gen_iwmmxt_shift gen_iwmmxt_shift_aarch64eb
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#define gen_jmp gen_jmp_aarch64eb
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#define gen_jmp gen_jmp_aarch64eb
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@ -3437,6 +3435,7 @@
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#define ARM64_REGS_STORAGE_SIZE ARM64_REGS_STORAGE_SIZE_aarch64eb
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#define ARM64_REGS_STORAGE_SIZE ARM64_REGS_STORAGE_SIZE_aarch64eb
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#define aarch64_cpu_do_interrupt aarch64_cpu_do_interrupt_aarch64eb
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#define aarch64_cpu_do_interrupt aarch64_cpu_do_interrupt_aarch64eb
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#define aarch64_cpu_register_types aarch64_cpu_register_types_aarch64eb
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#define aarch64_cpu_register_types aarch64_cpu_register_types_aarch64eb
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#define aarch64_translator_ops aarch64_translator_ops_aarch64eb
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#define arm64_reg_read arm64_reg_read_aarch64eb
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#define arm64_reg_read arm64_reg_read_aarch64eb
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#define arm64_reg_reset arm64_reg_reset_aarch64eb
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#define arm64_reg_reset arm64_reg_reset_aarch64eb
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#define arm64_reg_write arm64_reg_write_aarch64eb
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#define arm64_reg_write arm64_reg_write_aarch64eb
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@ -44,6 +44,8 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
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db->singlestep_enabled = cpu->singlestep_enabled;
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db->singlestep_enabled = cpu->singlestep_enabled;
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db->uc = cpu->uc;
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db->uc = cpu->uc;
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db->uc->block_full = false;
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/* Instruction counting */
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/* Instruction counting */
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max_insns = db->tb->cflags & CF_COUNT_MASK;
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max_insns = db->tb->cflags & CF_COUNT_MASK;
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if (max_insns == 0) {
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if (max_insns == 0) {
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@ -63,6 +65,26 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
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/* Reset the temp count so that we can identify leaks */
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/* Reset the temp count so that we can identify leaks */
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tcg_clear_temp_count();
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tcg_clear_temp_count();
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/* Unicorn: early check to see if the address of this block is
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* the "run until" address. */
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if (tb->pc == cpu->uc->addr_end) {
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gen_tb_start(tcg_ctx, tb);
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goto tb_end;
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}
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/* Unicorn: trace this block on request
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* Only hook this block if it is not broken from previous translation due to
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* full translation cache
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*/
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if (!cpu->uc->block_full && HOOK_EXISTS_BOUNDED(cpu->uc, UC_HOOK_BLOCK, db->pc_first)) {
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// Save block address to see if we need to patch block size later
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cpu->uc->block_addr = db->pc_first;
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cpu->uc->size_arg = tcg_ctx->gen_op_buf[tcg_ctx->gen_op_buf[0].prev].args;
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gen_uc_tracecode(tcg_ctx, 0xf8f8f8f8, UC_HOOK_BLOCK_IDX, cpu->uc, db->pc_first);
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} else {
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cpu->uc->size_arg = -1;
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}
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/* Start translating. */
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/* Start translating. */
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gen_tb_start(tcg_ctx, db->tb);
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gen_tb_start(tcg_ctx, db->tb);
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ops->tb_start(db, cpu);
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ops->tb_start(db, cpu);
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@ -119,6 +141,7 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
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}
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}
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}
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}
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tb_end:
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/* Emit code to exit the TB, as indicated by db->is_jmp. */
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/* Emit code to exit the TB, as indicated by db->is_jmp. */
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ops->tb_stop(db, cpu);
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ops->tb_stop(db, cpu);
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gen_tb_end(tcg_ctx, db->tb, db->num_insns);
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gen_tb_end(tcg_ctx, db->tb, db->num_insns);
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@ -1166,8 +1166,6 @@
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#define gen_helper_yield gen_helper_yield_arm
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#define gen_helper_yield gen_helper_yield_arm
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#define gen_hvc gen_hvc_arm
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#define gen_hvc gen_hvc_arm
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#define gen_intermediate_code gen_intermediate_code_arm
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#define gen_intermediate_code gen_intermediate_code_arm
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#define gen_intermediate_code gen_intermediate_code_arm
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#define gen_intermediate_code_a64 gen_intermediate_code_a64_arm
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#define gen_iwmmxt_address gen_iwmmxt_address_arm
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#define gen_iwmmxt_address gen_iwmmxt_address_arm
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#define gen_iwmmxt_shift gen_iwmmxt_shift_arm
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#define gen_iwmmxt_shift gen_iwmmxt_shift_arm
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#define gen_jmp gen_jmp_arm
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#define gen_jmp gen_jmp_arm
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@ -3434,6 +3432,7 @@
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#define xpsr_write xpsr_write_arm
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#define xpsr_write xpsr_write_arm
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#define xscale_cp_reginfo xscale_cp_reginfo_arm
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#define xscale_cp_reginfo xscale_cp_reginfo_arm
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#define xscale_cpar_write xscale_cpar_write_arm
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#define xscale_cpar_write xscale_cpar_write_arm
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#define aarch64_translator_ops aarch64_translator_ops_arm
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#define ARM_REGS_STORAGE_SIZE ARM_REGS_STORAGE_SIZE_arm
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#define ARM_REGS_STORAGE_SIZE ARM_REGS_STORAGE_SIZE_arm
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#define arm_regime_tbi0 arm_regime_tbi0_arm
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#define arm_regime_tbi0 arm_regime_tbi0_arm
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#define arm_regime_tbi1 arm_regime_tbi1_arm
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#define arm_regime_tbi1 arm_regime_tbi1_arm
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@ -1166,8 +1166,6 @@
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#define gen_helper_yield gen_helper_yield_armeb
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#define gen_helper_yield gen_helper_yield_armeb
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#define gen_hvc gen_hvc_armeb
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#define gen_hvc gen_hvc_armeb
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#define gen_intermediate_code gen_intermediate_code_armeb
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#define gen_intermediate_code gen_intermediate_code_armeb
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#define gen_intermediate_code gen_intermediate_code_armeb
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#define gen_intermediate_code_a64 gen_intermediate_code_a64_armeb
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#define gen_iwmmxt_address gen_iwmmxt_address_armeb
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#define gen_iwmmxt_address gen_iwmmxt_address_armeb
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#define gen_iwmmxt_shift gen_iwmmxt_shift_armeb
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#define gen_iwmmxt_shift gen_iwmmxt_shift_armeb
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#define gen_jmp gen_jmp_armeb
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#define gen_jmp gen_jmp_armeb
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@ -3434,6 +3432,7 @@
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#define xpsr_write xpsr_write_armeb
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#define xpsr_write xpsr_write_armeb
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#define xscale_cp_reginfo xscale_cp_reginfo_armeb
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#define xscale_cp_reginfo xscale_cp_reginfo_armeb
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#define xscale_cpar_write xscale_cpar_write_armeb
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#define xscale_cpar_write xscale_cpar_write_armeb
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#define aarch64_translator_ops aarch64_translator_ops_armeb
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#define ARM_REGS_STORAGE_SIZE ARM_REGS_STORAGE_SIZE_armeb
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#define ARM_REGS_STORAGE_SIZE ARM_REGS_STORAGE_SIZE_armeb
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#define arm_regime_tbi0 arm_regime_tbi0_armeb
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#define arm_regime_tbi0 arm_regime_tbi0_armeb
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#define arm_regime_tbi1 arm_regime_tbi1_armeb
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#define arm_regime_tbi1 arm_regime_tbi1_armeb
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@ -1172,8 +1172,6 @@ symbols = (
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'gen_helper_yield',
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'gen_helper_yield',
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'gen_hvc',
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'gen_hvc',
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'gen_intermediate_code',
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'gen_intermediate_code',
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'gen_intermediate_code',
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'gen_intermediate_code_a64',
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'gen_iwmmxt_address',
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'gen_iwmmxt_address',
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'gen_iwmmxt_shift',
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'gen_iwmmxt_shift',
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'gen_jmp',
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'gen_jmp',
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@ -3443,6 +3441,7 @@ symbols = (
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)
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)
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arm_symbols = (
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arm_symbols = (
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'aarch64_translator_ops',
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'ARM_REGS_STORAGE_SIZE',
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'ARM_REGS_STORAGE_SIZE',
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'arm_regime_tbi0',
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'arm_regime_tbi0',
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'arm_regime_tbi1',
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'arm_regime_tbi1',
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@ -3456,6 +3455,7 @@ aarch64_symbols = (
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'ARM64_REGS_STORAGE_SIZE',
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'ARM64_REGS_STORAGE_SIZE',
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'aarch64_cpu_do_interrupt',
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'aarch64_cpu_do_interrupt',
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'aarch64_cpu_register_types',
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'aarch64_cpu_register_types',
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'aarch64_translator_ops',
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'arm64_reg_read',
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'arm64_reg_read',
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'arm64_reg_reset',
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'arm64_reg_reset',
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'arm64_reg_write',
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'arm64_reg_write',
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@ -1166,8 +1166,6 @@
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#define gen_helper_yield gen_helper_yield_m68k
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#define gen_helper_yield gen_helper_yield_m68k
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#define gen_hvc gen_hvc_m68k
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#define gen_hvc gen_hvc_m68k
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#define gen_intermediate_code gen_intermediate_code_m68k
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#define gen_intermediate_code gen_intermediate_code_m68k
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#define gen_intermediate_code gen_intermediate_code_m68k
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#define gen_intermediate_code_a64 gen_intermediate_code_a64_m68k
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#define gen_iwmmxt_address gen_iwmmxt_address_m68k
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#define gen_iwmmxt_address gen_iwmmxt_address_m68k
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#define gen_iwmmxt_shift gen_iwmmxt_shift_m68k
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#define gen_iwmmxt_shift gen_iwmmxt_shift_m68k
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#define gen_jmp gen_jmp_m68k
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#define gen_jmp gen_jmp_m68k
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@ -1166,8 +1166,6 @@
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#define gen_helper_yield gen_helper_yield_mips
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#define gen_helper_yield gen_helper_yield_mips
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#define gen_hvc gen_hvc_mips
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#define gen_hvc gen_hvc_mips
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#define gen_intermediate_code gen_intermediate_code_mips
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#define gen_intermediate_code gen_intermediate_code_mips
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#define gen_intermediate_code gen_intermediate_code_mips
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#define gen_intermediate_code_a64 gen_intermediate_code_a64_mips
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#define gen_iwmmxt_address gen_iwmmxt_address_mips
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#define gen_iwmmxt_address gen_iwmmxt_address_mips
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#define gen_iwmmxt_shift gen_iwmmxt_shift_mips
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#define gen_iwmmxt_shift gen_iwmmxt_shift_mips
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#define gen_jmp gen_jmp_mips
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#define gen_jmp gen_jmp_mips
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@ -1166,8 +1166,6 @@
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#define gen_helper_yield gen_helper_yield_mips64
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#define gen_helper_yield gen_helper_yield_mips64
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#define gen_hvc gen_hvc_mips64
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#define gen_hvc gen_hvc_mips64
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#define gen_intermediate_code gen_intermediate_code_mips64
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#define gen_intermediate_code gen_intermediate_code_mips64
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#define gen_intermediate_code gen_intermediate_code_mips64
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#define gen_intermediate_code_a64 gen_intermediate_code_a64_mips64
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#define gen_iwmmxt_address gen_iwmmxt_address_mips64
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#define gen_iwmmxt_address gen_iwmmxt_address_mips64
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#define gen_iwmmxt_shift gen_iwmmxt_shift_mips64
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#define gen_iwmmxt_shift gen_iwmmxt_shift_mips64
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#define gen_jmp gen_jmp_mips64
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#define gen_jmp gen_jmp_mips64
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@ -1166,8 +1166,6 @@
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#define gen_helper_yield gen_helper_yield_mips64el
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#define gen_helper_yield gen_helper_yield_mips64el
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#define gen_hvc gen_hvc_mips64el
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#define gen_hvc gen_hvc_mips64el
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#define gen_intermediate_code gen_intermediate_code_mips64el
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#define gen_intermediate_code gen_intermediate_code_mips64el
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#define gen_intermediate_code gen_intermediate_code_mips64el
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#define gen_intermediate_code_a64 gen_intermediate_code_a64_mips64el
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#define gen_iwmmxt_address gen_iwmmxt_address_mips64el
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#define gen_iwmmxt_address gen_iwmmxt_address_mips64el
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#define gen_iwmmxt_shift gen_iwmmxt_shift_mips64el
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#define gen_iwmmxt_shift gen_iwmmxt_shift_mips64el
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#define gen_jmp gen_jmp_mips64el
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#define gen_jmp gen_jmp_mips64el
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@ -1166,8 +1166,6 @@
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#define gen_helper_yield gen_helper_yield_mipsel
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#define gen_helper_yield gen_helper_yield_mipsel
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#define gen_hvc gen_hvc_mipsel
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#define gen_hvc gen_hvc_mipsel
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#define gen_intermediate_code gen_intermediate_code_mipsel
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#define gen_intermediate_code gen_intermediate_code_mipsel
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#define gen_intermediate_code gen_intermediate_code_mipsel
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#define gen_intermediate_code_a64 gen_intermediate_code_a64_mipsel
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#define gen_iwmmxt_address gen_iwmmxt_address_mipsel
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#define gen_iwmmxt_address gen_iwmmxt_address_mipsel
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#define gen_iwmmxt_shift gen_iwmmxt_shift_mipsel
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#define gen_iwmmxt_shift gen_iwmmxt_shift_mipsel
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#define gen_jmp gen_jmp_mipsel
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#define gen_jmp gen_jmp_mipsel
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@ -1166,8 +1166,6 @@
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#define gen_helper_yield gen_helper_yield_powerpc
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#define gen_helper_yield gen_helper_yield_powerpc
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#define gen_hvc gen_hvc_powerpc
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#define gen_hvc gen_hvc_powerpc
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#define gen_intermediate_code gen_intermediate_code_powerpc
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#define gen_intermediate_code gen_intermediate_code_powerpc
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#define gen_intermediate_code gen_intermediate_code_powerpc
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#define gen_intermediate_code_a64 gen_intermediate_code_a64_powerpc
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#define gen_iwmmxt_address gen_iwmmxt_address_powerpc
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#define gen_iwmmxt_address gen_iwmmxt_address_powerpc
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#define gen_iwmmxt_shift gen_iwmmxt_shift_powerpc
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#define gen_iwmmxt_shift gen_iwmmxt_shift_powerpc
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#define gen_jmp gen_jmp_powerpc
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#define gen_jmp gen_jmp_powerpc
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@ -1166,8 +1166,6 @@
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#define gen_helper_yield gen_helper_yield_sparc
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#define gen_helper_yield gen_helper_yield_sparc
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#define gen_hvc gen_hvc_sparc
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#define gen_hvc gen_hvc_sparc
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#define gen_intermediate_code gen_intermediate_code_sparc
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#define gen_intermediate_code gen_intermediate_code_sparc
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#define gen_intermediate_code gen_intermediate_code_sparc
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#define gen_intermediate_code_a64 gen_intermediate_code_a64_sparc
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#define gen_iwmmxt_address gen_iwmmxt_address_sparc
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#define gen_iwmmxt_address gen_iwmmxt_address_sparc
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#define gen_iwmmxt_shift gen_iwmmxt_shift_sparc
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#define gen_iwmmxt_shift gen_iwmmxt_shift_sparc
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#define gen_jmp gen_jmp_sparc
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#define gen_jmp gen_jmp_sparc
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@ -1166,8 +1166,6 @@
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#define gen_helper_yield gen_helper_yield_sparc64
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#define gen_helper_yield gen_helper_yield_sparc64
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#define gen_hvc gen_hvc_sparc64
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#define gen_hvc gen_hvc_sparc64
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||||||
#define gen_intermediate_code gen_intermediate_code_sparc64
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#define gen_intermediate_code gen_intermediate_code_sparc64
|
||||||
#define gen_intermediate_code gen_intermediate_code_sparc64
|
|
||||||
#define gen_intermediate_code_a64 gen_intermediate_code_a64_sparc64
|
|
||||||
#define gen_iwmmxt_address gen_iwmmxt_address_sparc64
|
#define gen_iwmmxt_address gen_iwmmxt_address_sparc64
|
||||||
#define gen_iwmmxt_shift gen_iwmmxt_shift_sparc64
|
#define gen_iwmmxt_shift gen_iwmmxt_shift_sparc64
|
||||||
#define gen_jmp gen_jmp_sparc64
|
#define gen_jmp gen_jmp_sparc64
|
||||||
|
|
|
@ -11509,6 +11509,11 @@ static int aarch64_tr_init_disas_context(DisasContextBase *dcbase,
|
||||||
return max_insns;
|
return max_insns;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu)
|
||||||
|
{
|
||||||
|
tcg_clear_temp_count();
|
||||||
|
}
|
||||||
|
|
||||||
static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
|
static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
|
||||||
{
|
{
|
||||||
DisasContext *dc = container_of(dcbase, DisasContext, base);
|
DisasContext *dc = container_of(dcbase, DisasContext, base);
|
||||||
|
@ -11574,6 +11579,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
|
||||||
}
|
}
|
||||||
|
|
||||||
dc->base.pc_next = dc->pc;
|
dc->base.pc_next = dc->pc;
|
||||||
|
translator_loop_temp_check(&dc->base);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
|
static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
|
||||||
|
@ -11641,6 +11647,9 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* Functions above can change dc->pc, so re-align db->pc_next */
|
||||||
|
dc->base.pc_next = dc->pc;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void aarch64_tr_disas_log(const DisasContextBase *dcbase,
|
static void aarch64_tr_disas_log(const DisasContextBase *dcbase,
|
||||||
|
@ -11656,124 +11665,12 @@ static void aarch64_tr_disas_log(const DisasContextBase *dcbase,
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,
|
const TranslatorOps aarch64_translator_ops = {
|
||||||
TranslationBlock *tb)
|
aarch64_tr_init_disas_context,
|
||||||
{
|
aarch64_tr_tb_start,
|
||||||
CPUARMState *env = cs->env_ptr;
|
aarch64_tr_insn_start,
|
||||||
TCGContext *tcg_ctx = env->uc->tcg_ctx;
|
aarch64_tr_breakpoint_check,
|
||||||
DisasContext *dc = container_of(dcbase, DisasContext, base);
|
aarch64_tr_translate_insn,
|
||||||
int max_insns;
|
aarch64_tr_tb_stop,
|
||||||
|
aarch64_tr_disas_log,
|
||||||
dc->base.tb = tb;
|
};
|
||||||
dc->base.pc_first = dc->base.tb->pc;
|
|
||||||
dc->base.pc_next = dc->base.pc_first;
|
|
||||||
dc->base.is_jmp = DISAS_NEXT;
|
|
||||||
dc->base.num_insns = 0;
|
|
||||||
dc->base.singlestep_enabled = cs->singlestep_enabled;
|
|
||||||
|
|
||||||
env->uc->block_full = false;
|
|
||||||
|
|
||||||
max_insns = dc->base.tb->cflags & CF_COUNT_MASK;
|
|
||||||
if (max_insns == 0) {
|
|
||||||
max_insns = CF_COUNT_MASK;
|
|
||||||
}
|
|
||||||
if (max_insns > TCG_MAX_INSNS) {
|
|
||||||
max_insns = TCG_MAX_INSNS;
|
|
||||||
}
|
|
||||||
max_insns = aarch64_tr_init_disas_context(&dc->base, cs, max_insns);
|
|
||||||
|
|
||||||
tcg_clear_temp_count();
|
|
||||||
|
|
||||||
// Unicorn: early check to see if the address of this block is the until address
|
|
||||||
if (tb->pc == env->uc->addr_end) {
|
|
||||||
// imitate WFI instruction to halt emulation
|
|
||||||
gen_tb_start(tcg_ctx, tb);
|
|
||||||
dc->base.is_jmp = DISAS_WFI;
|
|
||||||
goto tb_end;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Unicorn: trace this block on request
|
|
||||||
// Only hook this block if it is not broken from previous translation due to
|
|
||||||
// full translation cache
|
|
||||||
if (!env->uc->block_full && HOOK_EXISTS_BOUNDED(env->uc, UC_HOOK_BLOCK, dc->base.pc_first)) {
|
|
||||||
// save block address to see if we need to patch block size later
|
|
||||||
env->uc->block_addr = dc->base.pc_first;
|
|
||||||
env->uc->size_arg = tcg_ctx->gen_op_buf[tcg_ctx->gen_op_buf[0].prev].args;
|
|
||||||
gen_uc_tracecode(tcg_ctx, 0xf8f8f8f8, UC_HOOK_BLOCK_IDX, env->uc, dc->base.pc_first);
|
|
||||||
} else {
|
|
||||||
env->uc->size_arg = -1;
|
|
||||||
}
|
|
||||||
|
|
||||||
gen_tb_start(tcg_ctx, tb);
|
|
||||||
|
|
||||||
do {
|
|
||||||
dc->base.num_insns++;
|
|
||||||
aarch64_tr_insn_start(&dc->base, cs);
|
|
||||||
|
|
||||||
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
|
|
||||||
CPUBreakpoint *bp;
|
|
||||||
QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
|
|
||||||
if (bp->pc == dc->base.pc_next) {
|
|
||||||
if (aarch64_tr_breakpoint_check(&dc->base, cs, bp)) {
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (dc->base.is_jmp > DISAS_TOO_MANY) {
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
//if (dc->base.num_insns == max_insns && (dc->base.tb->cflags & CF_LAST_IO)) {
|
|
||||||
// gen_io_start();
|
|
||||||
//}
|
|
||||||
|
|
||||||
aarch64_tr_translate_insn(&dc->base, cs);
|
|
||||||
|
|
||||||
if (tcg_check_temp_count()) {
|
|
||||||
fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n",
|
|
||||||
dc->pc);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!dc->base.is_jmp && (tcg_op_buf_full(tcg_ctx) || cs->singlestep_enabled ||
|
|
||||||
/* Unicorn: commented out: singlestep ||*/ dc->base.num_insns >= max_insns)) {
|
|
||||||
dc->base.is_jmp = DISAS_TOO_MANY;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Translation stops when a conditional branch is encountered.
|
|
||||||
* Otherwise the subsequent code could get translated several times.
|
|
||||||
* Also stop translation when a page boundary is reached. This
|
|
||||||
* ensures prefetch aborts occur at the right place.
|
|
||||||
*/
|
|
||||||
} while (!dc->base.is_jmp);
|
|
||||||
|
|
||||||
/* if too long translation, save this info */
|
|
||||||
if (tcg_op_buf_full(tcg_ctx) || dc->base.num_insns >= max_insns) {
|
|
||||||
env->uc->block_full = true;
|
|
||||||
}
|
|
||||||
|
|
||||||
//if (dc->base.tb->cflags & CF_LAST_IO) {
|
|
||||||
// gen_io_end();
|
|
||||||
//}
|
|
||||||
|
|
||||||
tb_end:
|
|
||||||
aarch64_tr_tb_stop(&dc->base, cs);
|
|
||||||
|
|
||||||
gen_tb_end(tcg_ctx, tb, dc->base.num_insns);
|
|
||||||
|
|
||||||
dc->base.tb->size = dc->pc - dc->base.pc_first;
|
|
||||||
dc->base.tb->icount = dc->base.num_insns;
|
|
||||||
|
|
||||||
// Unicorn: commented out
|
|
||||||
#ifdef DEBUG_DISAS
|
|
||||||
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) &&
|
|
||||||
qemu_log_in_addr_range(dc->base.pc_first)) {
|
|
||||||
//qemu_log_lock();
|
|
||||||
qemu_log("----------------\n");
|
|
||||||
//qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first));
|
|
||||||
aarch64_tr_disas_log(&dc->base, cs);
|
|
||||||
qemu_log("\n");
|
|
||||||
//qemu_log_unlock();
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
|
@ -12147,6 +12147,8 @@ static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
|
||||||
tcg_gen_movi_i32(tcg_ctx, tmp, 0);
|
tcg_gen_movi_i32(tcg_ctx, tmp, 0);
|
||||||
store_cpu_field(tcg_ctx, tmp, condexec_bits);
|
store_cpu_field(tcg_ctx, tmp, condexec_bits);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
tcg_clear_temp_count();
|
||||||
}
|
}
|
||||||
|
|
||||||
static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
|
static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
|
||||||
|
@ -12269,6 +12271,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
|
||||||
}
|
}
|
||||||
|
|
||||||
dc->base.pc_next = dc->pc;
|
dc->base.pc_next = dc->pc;
|
||||||
|
translator_loop_temp_check(&dc->base);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
|
static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
|
||||||
|
@ -12384,6 +12387,8 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
|
||||||
gen_goto_tb(dc, 1, dc->pc);
|
gen_goto_tb(dc, 1, dc->pc);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
/* Functions above can change dc->pc, so re-align db->pc_next */
|
||||||
|
dc->base.pc_next = dc->pc;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void arm_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
|
static void arm_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
|
||||||
|
@ -12398,133 +12403,29 @@ static void arm_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static const TranslatorOps arm_translator_ops = {
|
||||||
|
arm_tr_init_disas_context,
|
||||||
|
arm_tr_tb_start,
|
||||||
|
arm_tr_insn_start,
|
||||||
|
arm_tr_breakpoint_check,
|
||||||
|
arm_tr_translate_insn,
|
||||||
|
arm_tr_tb_stop,
|
||||||
|
arm_tr_disas_log,
|
||||||
|
};
|
||||||
|
|
||||||
/* generate intermediate code for basic block 'tb'. */
|
/* generate intermediate code for basic block 'tb'. */
|
||||||
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
|
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
|
||||||
{
|
{
|
||||||
DisasContext dc1, *dc = &dc1;
|
DisasContext dc;
|
||||||
CPUARMState *env = cs->env_ptr;
|
const TranslatorOps *ops = &arm_translator_ops;
|
||||||
TCGContext *tcg_ctx = cs->uc->tcg_ctx;
|
|
||||||
int max_insns;
|
|
||||||
|
|
||||||
/* generate intermediate code */
|
#ifdef TARGET_AARCH64
|
||||||
|
|
||||||
/* The A64 decoder has its own top level loop, because it doesn't need
|
|
||||||
* the A32/T32 complexity to do with conditional execution/IT blocks/etc.
|
|
||||||
*/
|
|
||||||
if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
|
if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
|
||||||
gen_intermediate_code_a64(&dc->base, cs, tb);
|
ops = &aarch64_translator_ops;
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
dc->base.tb = tb;
|
|
||||||
dc->base.pc_first = dc->base.tb->pc;
|
|
||||||
dc->base.pc_next = dc->base.pc_first;
|
|
||||||
dc->base.is_jmp = DISAS_NEXT;
|
|
||||||
dc->base.num_insns = 0;
|
|
||||||
dc->base.singlestep_enabled = cs->singlestep_enabled;
|
|
||||||
|
|
||||||
env->uc->block_full = false;
|
|
||||||
|
|
||||||
max_insns = tb->cflags & CF_COUNT_MASK;
|
|
||||||
if (max_insns == 0) {
|
|
||||||
max_insns = CF_COUNT_MASK;
|
|
||||||
}
|
|
||||||
if (max_insns > TCG_MAX_INSNS) {
|
|
||||||
max_insns = TCG_MAX_INSNS;
|
|
||||||
}
|
|
||||||
max_insns = arm_tr_init_disas_context(&dc->base, cs, max_insns);
|
|
||||||
|
|
||||||
gen_tb_start(tcg_ctx, tb);
|
|
||||||
|
|
||||||
tcg_clear_temp_count();
|
|
||||||
arm_tr_tb_start(&dc->base, cs);
|
|
||||||
|
|
||||||
// Unicorn: early check to see if the address of this block is the until address
|
|
||||||
if (tb->pc == env->uc->addr_end) {
|
|
||||||
// imitate WFI instruction to halt emulation
|
|
||||||
gen_tb_start(tcg_ctx, tb);
|
|
||||||
dc->base.is_jmp = DISAS_WFI;
|
|
||||||
goto tb_end;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Unicorn: trace this block on request
|
|
||||||
// Only hook this block if it is not broken from previous translation due to
|
|
||||||
// full translation cache
|
|
||||||
if (!env->uc->block_full && HOOK_EXISTS_BOUNDED(env->uc, UC_HOOK_BLOCK, dc->base.pc_first)) {
|
|
||||||
// save block address to see if we need to patch block size later
|
|
||||||
env->uc->block_addr = dc->base.pc_first;
|
|
||||||
env->uc->size_arg = tcg_ctx->gen_op_buf[tcg_ctx->gen_op_buf[0].prev].args;
|
|
||||||
gen_uc_tracecode(tcg_ctx, 0xf8f8f8f8, UC_HOOK_BLOCK_IDX, env->uc, dc->base.pc_first);
|
|
||||||
} else {
|
|
||||||
env->uc->size_arg = -1;
|
|
||||||
}
|
|
||||||
|
|
||||||
do {
|
|
||||||
dc->base.num_insns++;
|
|
||||||
arm_tr_insn_start(&dc->base, cs);
|
|
||||||
|
|
||||||
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
|
|
||||||
CPUBreakpoint *bp;
|
|
||||||
QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
|
|
||||||
if (bp->pc == dc->base.pc_next) {
|
|
||||||
if (arm_tr_breakpoint_check(&dc->base, cs, bp)) {
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (dc->base.is_jmp > DISAS_TOO_MANY) {
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
// Unicorn: commented out
|
|
||||||
#if 0
|
|
||||||
if (dc->base.num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
|
|
||||||
gen_io_start();
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
arm_tr_translate_insn(&dc->base, cs);
|
|
||||||
|
|
||||||
if (tcg_check_temp_count()) {
|
|
||||||
fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n",
|
|
||||||
dc->pc);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!dc->base.is_jmp && (tcg_op_buf_full(tcg_ctx) || // singlestep || // Unicorn: commented out
|
|
||||||
dc->base.num_insns >= max_insns)) {
|
|
||||||
dc->base.is_jmp = DISAS_TOO_MANY;
|
|
||||||
env->uc->block_full = true;
|
|
||||||
}
|
|
||||||
} while (!dc->base.is_jmp);
|
|
||||||
|
|
||||||
// Unicorn: if'd out
|
|
||||||
#if 0
|
|
||||||
if (dc->base.tb->cflags & CF_LAST_IO) {
|
|
||||||
gen_io_end();
|
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
tb_end:
|
translator_loop(ops, &dc.base, cpu, tb);
|
||||||
arm_tr_tb_stop(&dc->base, cs);
|
|
||||||
|
|
||||||
gen_tb_end(tcg_ctx, tb, dc->base.num_insns);
|
|
||||||
|
|
||||||
tb->size = dc->pc - dc->base.pc_first;
|
|
||||||
tb->icount = dc->base.num_insns;
|
|
||||||
|
|
||||||
// Unicorn: commented out
|
|
||||||
#ifdef DEBUG_DISAS
|
|
||||||
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) &&
|
|
||||||
qemu_log_in_addr_range(dc->base.pc_first)) {
|
|
||||||
//qemu_log_lock();
|
|
||||||
qemu_log("----------------\n");
|
|
||||||
//qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first));
|
|
||||||
arm_tr_disas_log(&dc->base, cs);
|
|
||||||
qemu_log("\n");
|
|
||||||
//qemu_log_unlock();
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#if 0
|
#if 0
|
||||||
|
|
|
@ -149,19 +149,13 @@ static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
|
||||||
|
|
||||||
#ifdef TARGET_AARCH64
|
#ifdef TARGET_AARCH64
|
||||||
void a64_translate_init(struct uc_struct *uc);
|
void a64_translate_init(struct uc_struct *uc);
|
||||||
void gen_intermediate_code_a64(DisasContextBase *db, CPUState *cpu,
|
|
||||||
TranslationBlock *tb);
|
|
||||||
void gen_a64_set_pc_im(DisasContext *s, uint64_t val);
|
void gen_a64_set_pc_im(DisasContext *s, uint64_t val);
|
||||||
|
extern const TranslatorOps aarch64_translator_ops;
|
||||||
#else
|
#else
|
||||||
static inline void a64_translate_init(struct uc_struct *uc)
|
static inline void a64_translate_init(struct uc_struct *uc)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void gen_intermediate_code_a64(DisasContextBase *db, CPUState *cpu,
|
|
||||||
TranslationBlock *tb)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void gen_a64_set_pc_im(DisasContext *s, uint64_t val)
|
static inline void gen_a64_set_pc_im(DisasContext *s, uint64_t val)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
|
@ -1166,8 +1166,6 @@
|
||||||
#define gen_helper_yield gen_helper_yield_x86_64
|
#define gen_helper_yield gen_helper_yield_x86_64
|
||||||
#define gen_hvc gen_hvc_x86_64
|
#define gen_hvc gen_hvc_x86_64
|
||||||
#define gen_intermediate_code gen_intermediate_code_x86_64
|
#define gen_intermediate_code gen_intermediate_code_x86_64
|
||||||
#define gen_intermediate_code gen_intermediate_code_x86_64
|
|
||||||
#define gen_intermediate_code_a64 gen_intermediate_code_a64_x86_64
|
|
||||||
#define gen_iwmmxt_address gen_iwmmxt_address_x86_64
|
#define gen_iwmmxt_address gen_iwmmxt_address_x86_64
|
||||||
#define gen_iwmmxt_shift gen_iwmmxt_shift_x86_64
|
#define gen_iwmmxt_shift gen_iwmmxt_shift_x86_64
|
||||||
#define gen_jmp gen_jmp_x86_64
|
#define gen_jmp gen_jmp_x86_64
|
||||||
|
|
Loading…
Reference in a new issue