yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2024-12-23 05:05:36 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/arm: [tcg] Port to generic translation framework

Browse source 
Backports commit 2316922420da6fd0d1ffb5557d0cdcc5958bcf44 from qemu
This commit is contained in:
Lluís Vilanova 2018-03-04 20:11:49 -05:00 committed by Lioncash
parent cc00feb2df
commit 74d437827b
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
18 changed files with 69 additions and 276 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
qemu/aarch64.h
View file

@ -1166,8 +1166,6 @@
#define gen_helper_yield gen_helper_yield_aarch64
#define gen_hvc gen_hvc_aarch64
#define gen_intermediate_code gen_intermediate_code_aarch64
#define gen_intermediate_code gen_intermediate_code_aarch64
#define gen_intermediate_code_a64 gen_intermediate_code_a64_aarch64
#define gen_iwmmxt_address gen_iwmmxt_address_aarch64
#define gen_iwmmxt_shift gen_iwmmxt_shift_aarch64
#define gen_jmp gen_jmp_aarch64
@ -3437,6 +3435,7 @@
#define ARM64_REGS_STORAGE_SIZE ARM64_REGS_STORAGE_SIZE_aarch64
#define aarch64_cpu_do_interrupt aarch64_cpu_do_interrupt_aarch64
#define aarch64_cpu_register_types aarch64_cpu_register_types_aarch64
#define aarch64_translator_ops aarch64_translator_ops_aarch64
#define arm64_reg_read arm64_reg_read_aarch64
#define arm64_reg_reset arm64_reg_reset_aarch64
#define arm64_reg_write arm64_reg_write_aarch64

3
qemu/aarch64eb.h
View file

@ -1166,8 +1166,6 @@
#define gen_helper_yield gen_helper_yield_aarch64eb
#define gen_hvc gen_hvc_aarch64eb
#define gen_intermediate_code gen_intermediate_code_aarch64eb
#define gen_intermediate_code gen_intermediate_code_aarch64eb
#define gen_intermediate_code_a64 gen_intermediate_code_a64_aarch64eb
#define gen_iwmmxt_address gen_iwmmxt_address_aarch64eb
#define gen_iwmmxt_shift gen_iwmmxt_shift_aarch64eb
#define gen_jmp gen_jmp_aarch64eb
@ -3437,6 +3435,7 @@
#define ARM64_REGS_STORAGE_SIZE ARM64_REGS_STORAGE_SIZE_aarch64eb
#define aarch64_cpu_do_interrupt aarch64_cpu_do_interrupt_aarch64eb
#define aarch64_cpu_register_types aarch64_cpu_register_types_aarch64eb
#define aarch64_translator_ops aarch64_translator_ops_aarch64eb
#define arm64_reg_read arm64_reg_read_aarch64eb
#define arm64_reg_reset arm64_reg_reset_aarch64eb
#define arm64_reg_write arm64_reg_write_aarch64eb

23
qemu/accel/tcg/translator.c
View file

@ -44,6 +44,8 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
db->singlestep_enabled = cpu->singlestep_enabled;
db->uc = cpu->uc;
db->uc->block_full = false;
/* Instruction counting */
max_insns = db->tb->cflags & CF_COUNT_MASK;
if (max_insns == 0) {
@ -63,6 +65,26 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
/* Reset the temp count so that we can identify leaks */
tcg_clear_temp_count();
/* Unicorn: early check to see if the address of this block is
* the "run until" address. */
if (tb->pc == cpu->uc->addr_end) {
gen_tb_start(tcg_ctx, tb);
goto tb_end;
}
/* Unicorn: trace this block on request
* Only hook this block if it is not broken from previous translation due to
* full translation cache
*/
if (!cpu->uc->block_full && HOOK_EXISTS_BOUNDED(cpu->uc, UC_HOOK_BLOCK, db->pc_first)) {
// Save block address to see if we need to patch block size later
cpu->uc->block_addr = db->pc_first;
cpu->uc->size_arg = tcg_ctx->gen_op_buf[tcg_ctx->gen_op_buf[0].prev].args;
gen_uc_tracecode(tcg_ctx, 0xf8f8f8f8, UC_HOOK_BLOCK_IDX, cpu->uc, db->pc_first);
} else {
cpu->uc->size_arg = -1;
}
/* Start translating. */
gen_tb_start(tcg_ctx, db->tb);
ops->tb_start(db, cpu);
@ -119,6 +141,7 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
}
}
tb_end:
/* Emit code to exit the TB, as indicated by db->is_jmp. */
ops->tb_stop(db, cpu);
gen_tb_end(tcg_ctx, db->tb, db->num_insns);

3
qemu/arm.h
View file

@ -1166,8 +1166,6 @@
#define gen_helper_yield gen_helper_yield_arm
#define gen_hvc gen_hvc_arm
#define gen_intermediate_code gen_intermediate_code_arm
#define gen_intermediate_code gen_intermediate_code_arm
#define gen_intermediate_code_a64 gen_intermediate_code_a64_arm
#define gen_iwmmxt_address gen_iwmmxt_address_arm
#define gen_iwmmxt_shift gen_iwmmxt_shift_arm
#define gen_jmp gen_jmp_arm
@ -3434,6 +3432,7 @@
#define xpsr_write xpsr_write_arm
#define xscale_cp_reginfo xscale_cp_reginfo_arm
#define xscale_cpar_write xscale_cpar_write_arm
#define aarch64_translator_ops aarch64_translator_ops_arm
#define ARM_REGS_STORAGE_SIZE ARM_REGS_STORAGE_SIZE_arm
#define arm_regime_tbi0 arm_regime_tbi0_arm
#define arm_regime_tbi1 arm_regime_tbi1_arm

3
qemu/armeb.h
View file

@ -1166,8 +1166,6 @@
#define gen_helper_yield gen_helper_yield_armeb
#define gen_hvc gen_hvc_armeb
#define gen_intermediate_code gen_intermediate_code_armeb
#define gen_intermediate_code gen_intermediate_code_armeb
#define gen_intermediate_code_a64 gen_intermediate_code_a64_armeb
#define gen_iwmmxt_address gen_iwmmxt_address_armeb
#define gen_iwmmxt_shift gen_iwmmxt_shift_armeb
#define gen_jmp gen_jmp_armeb
@ -3434,6 +3432,7 @@
#define xpsr_write xpsr_write_armeb
#define xscale_cp_reginfo xscale_cp_reginfo_armeb
#define xscale_cpar_write xscale_cpar_write_armeb
#define aarch64_translator_ops aarch64_translator_ops_armeb
#define ARM_REGS_STORAGE_SIZE ARM_REGS_STORAGE_SIZE_armeb
#define arm_regime_tbi0 arm_regime_tbi0_armeb
#define arm_regime_tbi1 arm_regime_tbi1_armeb

4
qemu/header_gen.py
View file

@ -1172,8 +1172,6 @@ symbols = (
'gen_helper_yield',
'gen_hvc',
'gen_intermediate_code',
'gen_intermediate_code',
'gen_intermediate_code_a64',
'gen_iwmmxt_address',
'gen_iwmmxt_shift',
'gen_jmp',
@ -3443,6 +3441,7 @@ symbols = (
)
arm_symbols = (
'aarch64_translator_ops',
'ARM_REGS_STORAGE_SIZE',
'arm_regime_tbi0',
'arm_regime_tbi1',
@ -3456,6 +3455,7 @@ aarch64_symbols = (
'ARM64_REGS_STORAGE_SIZE',
'aarch64_cpu_do_interrupt',
'aarch64_cpu_register_types',
'aarch64_translator_ops',
'arm64_reg_read',
'arm64_reg_reset',
'arm64_reg_write',

2
qemu/m68k.h
View file

@ -1166,8 +1166,6 @@
#define gen_helper_yield gen_helper_yield_m68k
#define gen_hvc gen_hvc_m68k
#define gen_intermediate_code gen_intermediate_code_m68k
#define gen_intermediate_code gen_intermediate_code_m68k
#define gen_intermediate_code_a64 gen_intermediate_code_a64_m68k
#define gen_iwmmxt_address gen_iwmmxt_address_m68k
#define gen_iwmmxt_shift gen_iwmmxt_shift_m68k
#define gen_jmp gen_jmp_m68k

2
qemu/mips.h
View file

@ -1166,8 +1166,6 @@
#define gen_helper_yield gen_helper_yield_mips
#define gen_hvc gen_hvc_mips
#define gen_intermediate_code gen_intermediate_code_mips
#define gen_intermediate_code gen_intermediate_code_mips
#define gen_intermediate_code_a64 gen_intermediate_code_a64_mips
#define gen_iwmmxt_address gen_iwmmxt_address_mips
#define gen_iwmmxt_shift gen_iwmmxt_shift_mips
#define gen_jmp gen_jmp_mips

2
qemu/mips64.h
View file

@ -1166,8 +1166,6 @@
#define gen_helper_yield gen_helper_yield_mips64
#define gen_hvc gen_hvc_mips64
#define gen_intermediate_code gen_intermediate_code_mips64
#define gen_intermediate_code gen_intermediate_code_mips64
#define gen_intermediate_code_a64 gen_intermediate_code_a64_mips64
#define gen_iwmmxt_address gen_iwmmxt_address_mips64
#define gen_iwmmxt_shift gen_iwmmxt_shift_mips64
#define gen_jmp gen_jmp_mips64

2
qemu/mips64el.h
View file

@ -1166,8 +1166,6 @@
#define gen_helper_yield gen_helper_yield_mips64el
#define gen_hvc gen_hvc_mips64el
#define gen_intermediate_code gen_intermediate_code_mips64el
#define gen_intermediate_code gen_intermediate_code_mips64el
#define gen_intermediate_code_a64 gen_intermediate_code_a64_mips64el
#define gen_iwmmxt_address gen_iwmmxt_address_mips64el
#define gen_iwmmxt_shift gen_iwmmxt_shift_mips64el
#define gen_jmp gen_jmp_mips64el

2
qemu/mipsel.h
View file

@ -1166,8 +1166,6 @@
#define gen_helper_yield gen_helper_yield_mipsel
#define gen_hvc gen_hvc_mipsel
#define gen_intermediate_code gen_intermediate_code_mipsel
#define gen_intermediate_code gen_intermediate_code_mipsel
#define gen_intermediate_code_a64 gen_intermediate_code_a64_mipsel
#define gen_iwmmxt_address gen_iwmmxt_address_mipsel
#define gen_iwmmxt_shift gen_iwmmxt_shift_mipsel
#define gen_jmp gen_jmp_mipsel

2
qemu/powerpc.h
View file

@ -1166,8 +1166,6 @@
#define gen_helper_yield gen_helper_yield_powerpc
#define gen_hvc gen_hvc_powerpc
#define gen_intermediate_code gen_intermediate_code_powerpc
#define gen_intermediate_code gen_intermediate_code_powerpc
#define gen_intermediate_code_a64 gen_intermediate_code_a64_powerpc
#define gen_iwmmxt_address gen_iwmmxt_address_powerpc
#define gen_iwmmxt_shift gen_iwmmxt_shift_powerpc
#define gen_jmp gen_jmp_powerpc

2
qemu/sparc.h
View file

@ -1166,8 +1166,6 @@
#define gen_helper_yield gen_helper_yield_sparc
#define gen_hvc gen_hvc_sparc
#define gen_intermediate_code gen_intermediate_code_sparc
#define gen_intermediate_code gen_intermediate_code_sparc
#define gen_intermediate_code_a64 gen_intermediate_code_a64_sparc
#define gen_iwmmxt_address gen_iwmmxt_address_sparc
#define gen_iwmmxt_shift gen_iwmmxt_shift_sparc
#define gen_jmp gen_jmp_sparc

2
qemu/sparc64.h
View file

@ -1166,8 +1166,6 @@
#define gen_helper_yield gen_helper_yield_sparc64
#define gen_hvc gen_hvc_sparc64
#define gen_intermediate_code gen_intermediate_code_sparc64
#define gen_intermediate_code gen_intermediate_code_sparc64
#define gen_intermediate_code_a64 gen_intermediate_code_a64_sparc64
#define gen_iwmmxt_address gen_iwmmxt_address_sparc64
#define gen_iwmmxt_shift gen_iwmmxt_shift_sparc64
#define gen_jmp gen_jmp_sparc64

139
qemu/target/arm/translate-a64.c
View file

@ -11509,6 +11509,11 @@ static int aarch64_tr_init_disas_context(DisasContextBase *dcbase,
return max_insns;
}
static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu)
{
tcg_clear_temp_count();
}
static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
@ -11574,6 +11579,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
}
dc->base.pc_next = dc->pc;
translator_loop_temp_check(&dc->base);
}
static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
@ -11641,6 +11647,9 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
break;
}
}
/* Functions above can change dc->pc, so re-align db->pc_next */
dc->base.pc_next = dc->pc;
}
static void aarch64_tr_disas_log(const DisasContextBase *dcbase,
@ -11656,124 +11665,12 @@ static void aarch64_tr_disas_log(const DisasContextBase *dcbase,
#endif
}
void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,
TranslationBlock *tb)
{
CPUARMState *env = cs->env_ptr;
TCGContext *tcg_ctx = env->uc->tcg_ctx;
DisasContext *dc = container_of(dcbase, DisasContext, base);
int max_insns;
dc->base.tb = tb;
dc->base.pc_first = dc->base.tb->pc;
dc->base.pc_next = dc->base.pc_first;
dc->base.is_jmp = DISAS_NEXT;
dc->base.num_insns = 0;
dc->base.singlestep_enabled = cs->singlestep_enabled;
env->uc->block_full = false;
max_insns = dc->base.tb->cflags & CF_COUNT_MASK;
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
}
if (max_insns > TCG_MAX_INSNS) {
max_insns = TCG_MAX_INSNS;
}
max_insns = aarch64_tr_init_disas_context(&dc->base, cs, max_insns);
tcg_clear_temp_count();
// Unicorn: early check to see if the address of this block is the until address
if (tb->pc == env->uc->addr_end) {
// imitate WFI instruction to halt emulation
gen_tb_start(tcg_ctx, tb);
dc->base.is_jmp = DISAS_WFI;
goto tb_end;
}
// Unicorn: trace this block on request
// Only hook this block if it is not broken from previous translation due to
// full translation cache
if (!env->uc->block_full && HOOK_EXISTS_BOUNDED(env->uc, UC_HOOK_BLOCK, dc->base.pc_first)) {
// save block address to see if we need to patch block size later
env->uc->block_addr = dc->base.pc_first;
env->uc->size_arg = tcg_ctx->gen_op_buf[tcg_ctx->gen_op_buf[0].prev].args;
gen_uc_tracecode(tcg_ctx, 0xf8f8f8f8, UC_HOOK_BLOCK_IDX, env->uc, dc->base.pc_first);
} else {
env->uc->size_arg = -1;
}
gen_tb_start(tcg_ctx, tb);
do {
dc->base.num_insns++;
aarch64_tr_insn_start(&dc->base, cs);
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
CPUBreakpoint *bp;
QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
if (bp->pc == dc->base.pc_next) {
if (aarch64_tr_breakpoint_check(&dc->base, cs, bp)) {
break;
}
}
}
if (dc->base.is_jmp > DISAS_TOO_MANY) {
break;
}
}
//if (dc->base.num_insns == max_insns && (dc->base.tb->cflags & CF_LAST_IO)) {
// gen_io_start();
//}
aarch64_tr_translate_insn(&dc->base, cs);
if (tcg_check_temp_count()) {
fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n",
dc->pc);
}
if (!dc->base.is_jmp && (tcg_op_buf_full(tcg_ctx) || cs->singlestep_enabled ||
/* Unicorn: commented out: singlestep ||*/ dc->base.num_insns >= max_insns)) {
dc->base.is_jmp = DISAS_TOO_MANY;
}
/* Translation stops when a conditional branch is encountered.
* Otherwise the subsequent code could get translated several times.
* Also stop translation when a page boundary is reached. This
* ensures prefetch aborts occur at the right place.
*/
} while (!dc->base.is_jmp);
/* if too long translation, save this info */
if (tcg_op_buf_full(tcg_ctx) || dc->base.num_insns >= max_insns) {
env->uc->block_full = true;
}
//if (dc->base.tb->cflags & CF_LAST_IO) {
// gen_io_end();
//}
tb_end:
aarch64_tr_tb_stop(&dc->base, cs);
gen_tb_end(tcg_ctx, tb, dc->base.num_insns);
dc->base.tb->size = dc->pc - dc->base.pc_first;
dc->base.tb->icount = dc->base.num_insns;
// Unicorn: commented out
#ifdef DEBUG_DISAS
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) &&
qemu_log_in_addr_range(dc->base.pc_first)) {
//qemu_log_lock();
qemu_log("----------------\n");
//qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first));
aarch64_tr_disas_log(&dc->base, cs);
qemu_log("\n");
//qemu_log_unlock();
}
#endif
}
const TranslatorOps aarch64_translator_ops = {
aarch64_tr_init_disas_context,
aarch64_tr_tb_start,
aarch64_tr_insn_start,
aarch64_tr_breakpoint_check,
aarch64_tr_translate_insn,
aarch64_tr_tb_stop,
aarch64_tr_disas_log,
};

141
qemu/target/arm/translate.c
View file

@ -12147,6 +12147,8 @@ static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
tcg_gen_movi_i32(tcg_ctx, tmp, 0);
store_cpu_field(tcg_ctx, tmp, condexec_bits);
}
tcg_clear_temp_count();
}
static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
@ -12269,6 +12271,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
}
dc->base.pc_next = dc->pc;
translator_loop_temp_check(&dc->base);
}
static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
@ -12384,6 +12387,8 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
gen_goto_tb(dc, 1, dc->pc);
}
}
/* Functions above can change dc->pc, so re-align db->pc_next */
dc->base.pc_next = dc->pc;
}
static void arm_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
@ -12398,133 +12403,29 @@ static void arm_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
#endif
}
static const TranslatorOps arm_translator_ops = {
arm_tr_init_disas_context,
arm_tr_tb_start,
arm_tr_insn_start,
arm_tr_breakpoint_check,
arm_tr_translate_insn,
arm_tr_tb_stop,
arm_tr_disas_log,
};
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
{
DisasContext dc1, *dc = &dc1;
CPUARMState *env = cs->env_ptr;
TCGContext *tcg_ctx = cs->uc->tcg_ctx;
int max_insns;
DisasContext dc;
const TranslatorOps *ops = &arm_translator_ops;
/* generate intermediate code */
/* The A64 decoder has its own top level loop, because it doesn't need
* the A32/T32 complexity to do with conditional execution/IT blocks/etc.
*/
#ifdef TARGET_AARCH64
if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
gen_intermediate_code_a64(&dc->base, cs, tb);
return;
}
dc->base.tb = tb;
dc->base.pc_first = dc->base.tb->pc;
dc->base.pc_next = dc->base.pc_first;
dc->base.is_jmp = DISAS_NEXT;
dc->base.num_insns = 0;
dc->base.singlestep_enabled = cs->singlestep_enabled;
env->uc->block_full = false;
max_insns = tb->cflags & CF_COUNT_MASK;
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
}
if (max_insns > TCG_MAX_INSNS) {
max_insns = TCG_MAX_INSNS;
}
max_insns = arm_tr_init_disas_context(&dc->base, cs, max_insns);
gen_tb_start(tcg_ctx, tb);
tcg_clear_temp_count();
arm_tr_tb_start(&dc->base, cs);
// Unicorn: early check to see if the address of this block is the until address
if (tb->pc == env->uc->addr_end) {
// imitate WFI instruction to halt emulation
gen_tb_start(tcg_ctx, tb);
dc->base.is_jmp = DISAS_WFI;
goto tb_end;
}
// Unicorn: trace this block on request
// Only hook this block if it is not broken from previous translation due to
// full translation cache
if (!env->uc->block_full && HOOK_EXISTS_BOUNDED(env->uc, UC_HOOK_BLOCK, dc->base.pc_first)) {
// save block address to see if we need to patch block size later
env->uc->block_addr = dc->base.pc_first;
env->uc->size_arg = tcg_ctx->gen_op_buf[tcg_ctx->gen_op_buf[0].prev].args;
gen_uc_tracecode(tcg_ctx, 0xf8f8f8f8, UC_HOOK_BLOCK_IDX, env->uc, dc->base.pc_first);
} else {
env->uc->size_arg = -1;
}
do {
dc->base.num_insns++;
arm_tr_insn_start(&dc->base, cs);
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
CPUBreakpoint *bp;
QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
if (bp->pc == dc->base.pc_next) {
if (arm_tr_breakpoint_check(&dc->base, cs, bp)) {
break;
}
}
}
if (dc->base.is_jmp > DISAS_TOO_MANY) {
break;
}
}
// Unicorn: commented out
#if 0
if (dc->base.num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start();
}
#endif
arm_tr_translate_insn(&dc->base, cs);
if (tcg_check_temp_count()) {
fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n",
dc->pc);
}
if (!dc->base.is_jmp && (tcg_op_buf_full(tcg_ctx) || // singlestep || // Unicorn: commented out
dc->base.num_insns >= max_insns)) {
dc->base.is_jmp = DISAS_TOO_MANY;
env->uc->block_full = true;
}
} while (!dc->base.is_jmp);
// Unicorn: if'd out
#if 0
if (dc->base.tb->cflags & CF_LAST_IO) {
gen_io_end();
ops = &aarch64_translator_ops;
}
#endif
tb_end:
arm_tr_tb_stop(&dc->base, cs);
gen_tb_end(tcg_ctx, tb, dc->base.num_insns);
tb->size = dc->pc - dc->base.pc_first;
tb->icount = dc->base.num_insns;
// Unicorn: commented out
#ifdef DEBUG_DISAS
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) &&
qemu_log_in_addr_range(dc->base.pc_first)) {
//qemu_log_lock();
qemu_log("----------------\n");
//qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first));
arm_tr_disas_log(&dc->base, cs);
qemu_log("\n");
//qemu_log_unlock();
}
#endif
translator_loop(ops, &dc.base, cpu, tb);
}
#if 0

8
qemu/target/arm/translate.h
View file

@ -149,19 +149,13 @@ static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
#ifdef TARGET_AARCH64
void a64_translate_init(struct uc_struct *uc);
void gen_intermediate_code_a64(DisasContextBase *db, CPUState *cpu,
TranslationBlock *tb);
void gen_a64_set_pc_im(DisasContext *s, uint64_t val);
extern const TranslatorOps aarch64_translator_ops;
#else
static inline void a64_translate_init(struct uc_struct *uc)
{
}
static inline void gen_intermediate_code_a64(DisasContextBase *db, CPUState *cpu,
TranslationBlock *tb)
{
}
static inline void gen_a64_set_pc_im(DisasContext *s, uint64_t val)
{
}

2
qemu/x86_64.h
View file

@ -1166,8 +1166,6 @@
#define gen_helper_yield gen_helper_yield_x86_64
#define gen_hvc gen_hvc_x86_64
#define gen_intermediate_code gen_intermediate_code_x86_64
#define gen_intermediate_code gen_intermediate_code_x86_64
#define gen_intermediate_code_a64 gen_intermediate_code_a64_x86_64
#define gen_iwmmxt_address gen_iwmmxt_address_x86_64
#define gen_iwmmxt_shift gen_iwmmxt_shift_x86_64
#define gen_jmp gen_jmp_x86_64