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target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR

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Make the arm_cpu_dump_state() debug logging handle the M-profile XPSR
rather than assuming it's an A-profile CPSR. On M profile the PSR
line of a register dump will now look like this:

XPSR=41000000 -Z-- T priv-thread

Backports commit 5b906f3589443a3c69d8feeaac37263843ecfb8d from qemu
This commit is contained in:
Peter Maydell 2018-03-04 12:58:17 -05:00 committed by Lioncash
parent 9056a93c9a
commit 75f8224d13
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 5 additions and 18 deletions
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23
qemu/target/arm/translate.c
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@ -12440,7 +12440,6 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
ARMCPU *cpu = ARM_CPU(cs); ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env; CPUARMState *env = &cpu->env;
int i; int i;
const char *ns_status;
if (is_a64(env)) { if (is_a64(env)) {
aarch64_cpu_dump_state(cs, f, cpu_fprintf, flags); aarch64_cpu_dump_state(cs, f, cpu_fprintf, flags);
@ -12455,21 +12454,10 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
cpu_fprintf(f, " "); cpu_fprintf(f, " ");
} }
if (arm_feature(env, ARM_FEATURE_EL3) &&
(psr & CPSR_M) != ARM_CPU_MODE_MON) {
ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
} else {
ns_status = "";
}
if (arm_feature(env, ARM_FEATURE_M)) { if (arm_feature(env, ARM_FEATURE_M)) {
uint32_t xpsr = xpsr_read(env); uint32_t xpsr = xpsr_read(env);
const char *mode; const char *mode;
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
ns_status = env->v7m.secure ? "S " : "NS ";
}
if (xpsr & XPSR_EXCP) { if (xpsr & XPSR_EXCP) {
mode = "handler"; mode = "handler";
} else { } else {
@ -12480,14 +12468,13 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
} }
} }
cpu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", cpu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s\n",
xpsr, xpsr,
xpsr & XPSR_N ? 'N' : '-', xpsr & XPSR_N ? 'N' : '-',
xpsr & XPSR_Z ? 'Z' : '-', xpsr & XPSR_Z ? 'Z' : '-',
xpsr & XPSR_C ? 'C' : '-', xpsr & XPSR_C ? 'C' : '-',
xpsr & XPSR_V ? 'V' : '-', xpsr & XPSR_V ? 'V' : '-',
xpsr & XPSR_T ? 'T' : 'A', xpsr & XPSR_T ? 'T' : 'A',
ns_status,
mode); mode);
} else { } else {
uint32_t psr = cpsr_read(env); uint32_t psr = cpsr_read(env);
@ -12500,10 +12487,10 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
psr, psr,
psr & (1 << 31) ? 'N' : '-', psr & CPSR_N ? 'N' : '-',
psr & (1 << 30) ? 'Z' : '-', psr & CPSR_Z ? 'Z' : '-',
psr & (1 << 29) ? 'C' : '-', psr & CPSR_C ? 'C' : '-',
psr & (1 << 28) ? 'V' : '-', psr & CPSR_V ? 'V' : '-',
psr & CPSR_T ? 'T' : 'A', psr & CPSR_T ? 'T' : 'A',
ns_status, ns_status,
cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26); cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);