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target-mips: microMIPS32 R6 POOL16{A, C} instructions
microMIPS32 Release 6 POOL16A/ POOL16C instructions Backports commit ed7ce6c0f9d4370826557ce33d652beb88ccb3e6 from qemu
This commit is contained in:
Yongbok Kim
Lioncash
parent
6e6ca4dbd4
commit
76ab1f17fb
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@ -13264,6 +13264,112 @@ static void gen_pool16c_insn(DisasContext *ctx)
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}
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}
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static inline void gen_movep(DisasContext *ctx, int enc_dest, int enc_rt,
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int enc_rs)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGv **cpu_gpr = (TCGv **)tcg_ctx->cpu_gpr;
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int rd, rs, re, rt;
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static const int rd_enc[] = { 5, 5, 6, 4, 4, 4, 4, 4 };
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static const int re_enc[] = { 6, 7, 7, 21, 22, 5, 6, 7 };
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static const int rs_rt_enc[] = { 0, 17, 2, 3, 16, 18, 19, 20 };
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rd = rd_enc[enc_dest];
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re = re_enc[enc_dest];
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rs = rs_rt_enc[enc_rs];
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rt = rs_rt_enc[enc_rt];
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if (rs) {
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tcg_gen_mov_tl(tcg_ctx, *cpu_gpr[rd], *cpu_gpr[rs]);
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} else {
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tcg_gen_movi_tl(tcg_ctx, *cpu_gpr[rd], 0);
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}
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if (rt) {
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tcg_gen_mov_tl(tcg_ctx, *cpu_gpr[re], *cpu_gpr[rt]);
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} else {
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tcg_gen_movi_tl(tcg_ctx, *cpu_gpr[re], 0);
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}
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}
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static void gen_pool16c_r6_insn(DisasContext *ctx)
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{
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int rt = mmreg((ctx->opcode >> 7) & 0x7);
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int rs = mmreg((ctx->opcode >> 4) & 0x7);
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switch (ctx->opcode & 0xf) {
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case R6_NOT16:
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gen_logic(ctx, OPC_NOR, rt, rs, 0);
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break;
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case R6_AND16:
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gen_logic(ctx, OPC_AND, rt, rt, rs);
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break;
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case R6_LWM16:
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{
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int lwm_converted = 0x11 + extract32(ctx->opcode, 8, 2);
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int offset = extract32(ctx->opcode, 4, 4);
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gen_ldst_multiple(ctx, LWM32, lwm_converted, 29, offset << 2);
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}
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break;
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case R6_JRC16: /* JRCADDIUSP */
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if ((ctx->opcode >> 4) & 1) {
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/* JRCADDIUSP */
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int imm = extract32(ctx->opcode, 5, 5);
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gen_compute_branch(ctx, OPC_JR, 2, 31, 0, 0, 0);
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gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm << 2);
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} else {
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/* JRC16 */
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int rs = extract32(ctx->opcode, 5, 5);
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gen_compute_branch(ctx, OPC_JR, 2, rs, 0, 0, 0);
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}
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break;
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case MOVEP ... MOVEP_07:
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case MOVEP_0C ... MOVEP_0F:
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{
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int enc_dest = uMIPS_RD(ctx->opcode);
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int enc_rt = uMIPS_RS2(ctx->opcode);
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int enc_rs = (ctx->opcode & 3) | ((ctx->opcode >> 1) & 4);
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gen_movep(ctx, enc_dest, enc_rt, enc_rs);
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}
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break;
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case R6_XOR16:
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gen_logic(ctx, OPC_XOR, rt, rt, rs);
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break;
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case R6_OR16:
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gen_logic(ctx, OPC_OR, rt, rt, rs);
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break;
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case R6_SWM16:
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{
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int swm_converted = 0x11 + extract32(ctx->opcode, 8, 2);
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int offset = extract32(ctx->opcode, 4, 4);
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gen_ldst_multiple(ctx, SWM32, swm_converted, 29, offset << 2);
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}
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break;
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case JALRC16: /* BREAK16, SDBBP16 */
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switch (ctx->opcode & 0x3f) {
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case JALRC16:
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case JALRC16 + 0x20:
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/* JALRC16 */
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gen_compute_branch(ctx, OPC_JALR, 2, (ctx->opcode >> 5) & 0x1f,
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31, 0, 0);
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break;
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case R6_BREAK16:
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/* BREAK16 */
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generate_exception(ctx, EXCP_BREAK);
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break;
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case R6_SDBBP16:
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/* SDBBP16 */
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if (ctx->hflags & MIPS_HFLAG_SBRI) {
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generate_exception(ctx, EXCP_RI);
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} else {
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generate_exception(ctx, EXCP_DBp);
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}
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break;
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}
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break;
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default:
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generate_exception(ctx, EXCP_RI);
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break;
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}
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}
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static void gen_ldxs (DisasContext *ctx, int base, int index, int rd)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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@ -15284,7 +15390,14 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, bool *ins
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break;
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}
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gen_arith(ctx, opc, rd, rs1, rs2);
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if (ctx->insn_flags & ISA_MIPS32R6) {
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/* In the Release 6 the register number location in
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* the instruction encoding has changed.
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*/
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gen_arith(ctx, opc, rs1, rd, rs2);
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} else {
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gen_arith(ctx, opc, rd, rs1, rs2);
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}
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}
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break;
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case POOL16B:
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@ -15308,7 +15421,11 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, bool *ins
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}
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break;
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case POOL16C:
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gen_pool16c_insn(ctx);
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if (ctx->insn_flags & ISA_MIPS32R6) {
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gen_pool16c_r6_insn(ctx);
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} else {
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gen_pool16c_insn(ctx);
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}
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break;
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case LWGP16:
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{
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@ -15328,18 +15445,7 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, bool *ins
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int enc_dest = uMIPS_RD(ctx->opcode);
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int enc_rt = uMIPS_RS2(ctx->opcode);
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int enc_rs = uMIPS_RS1(ctx->opcode);
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int rd, rs, re, rt;
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static const int rd_enc[] = { 5, 5, 6, 4, 4, 4, 4, 4 };
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static const int re_enc[] = { 6, 7, 7, 21, 22, 5, 6, 7 };
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static const int rs_rt_enc[] = { 0, 17, 2, 3, 16, 18, 19, 20 };
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rd = rd_enc[enc_dest];
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re = re_enc[enc_dest];
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rs = rs_rt_enc[enc_rs];
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rt = rs_rt_enc[enc_rt];
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gen_arith(ctx, OPC_ADDU, rd, rs, 0);
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gen_arith(ctx, OPC_ADDU, re, rt, 0);
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gen_movep(ctx, enc_dest, enc_rt, enc_rs);
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}
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break;
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case LBU16:
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