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target/arm: Refactor disas_simd_indexed size checks
The integer size check was already outside of the opcode switch; move the floating-point size check outside as well. Unify the size vs index adjustment between fp and integer paths. Backports commit 449f264b1749ac0e59c58bbc2eacdb3dc302c2bf from qemu
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1fd2644738
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@ -11974,10 +11974,6 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
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case 0x05: /* FMLS */
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case 0x09: /* FMUL */
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case 0x19: /* FMULX */
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if (size == 1) {
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unallocated_encoding(s);
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return;
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}
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is_fp = true;
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break;
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default:
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@ -11988,45 +11984,48 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
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if (is_fp) {
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/* convert insn encoded size to TCGMemOp size */
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switch (size) {
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case 2: /* single precision */
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size = MO_32;
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index = h << 1 | l;
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rm |= (m << 4);
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break;
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case 3: /* double precision */
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size = MO_64;
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if (l || !is_q) {
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case 0: /* half-precision */
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if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
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unallocated_encoding(s);
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return;
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}
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index = h;
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rm |= (m << 4);
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break;
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case 0: /* half precision */
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size = MO_16;
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index = h << 2 | l << 1 | m;
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is_fp16 = true;
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if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
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break;
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}
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/* fallthru */
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default: /* unallocated */
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unallocated_encoding(s);
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return;
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}
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} else {
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switch (size) {
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case 1:
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index = h << 2 | l << 1 | m;
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break;
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case 2:
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index = h << 1 | l;
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rm |= (m << 4);
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case MO_32: /* single precision */
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case MO_64: /* double precision */
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break;
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default:
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unallocated_encoding(s);
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return;
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}
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} else {
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switch (size) {
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case MO_8:
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case MO_64:
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unallocated_encoding(s);
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return;
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}
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}
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/* Given TCGMemOp size, adjust register and indexing. */
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switch (size) {
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case MO_16:
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index = h << 2 | l << 1 | m;
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break;
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case MO_32:
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index = h << 1 | l;
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rm |= m << 4;
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break;
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case MO_64:
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if (l || !is_q) {
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unallocated_encoding(s);
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return;
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}
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index = h;
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rm |= m << 4;
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break;
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default:
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g_assert_not_reached();
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}
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if (!fp_access_check(s)) {
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