target/arm: Implement VLLDM for v7M CPUs with an FPU

Implement the VLLDM instruction for v7M for the FPU present cas.

Backports commit 956fe143b4f254356496a0a1c479fa632376dfec from qemu

qemu/aarch64.h

@@ -1749,6 +1749,7 @@
 #define helper_v7m_mrs helper_v7m_mrs_aarch64
 #define helper_v7m_msr helper_v7m_msr_aarch64
 #define helper_v7m_tt helper_v7m_tt_aarch64
+#define helper_v7m_vlldm helper_v7m_vlldm_aarch64
 #define helper_v7m_vlstm helper_v7m_vlstm_aarch64
 #define helper_v8m_stackcheck helper_v8m_stackcheck_aarch64
 #define helper_vfp_absd helper_vfp_absd_aarch64

qemu/aarch64eb.h

@@ -1749,6 +1749,7 @@
 #define helper_v7m_mrs helper_v7m_mrs_aarch64eb
 #define helper_v7m_msr helper_v7m_msr_aarch64eb
 #define helper_v7m_tt helper_v7m_tt_aarch64eb
+#define helper_v7m_vlldm helper_v7m_vlldm_aarch64eb
 #define helper_v7m_vlstm helper_v7m_vlstm_aarch64eb
 #define helper_v8m_stackcheck helper_v8m_stackcheck_aarch64eb
 #define helper_vfp_absd helper_vfp_absd_aarch64eb

qemu/arm.h

@@ -1749,6 +1749,7 @@
 #define helper_v7m_mrs helper_v7m_mrs_arm
 #define helper_v7m_msr helper_v7m_msr_arm
 #define helper_v7m_tt helper_v7m_tt_arm
+#define helper_v7m_vlldm helper_v7m_vlldm_arm
 #define helper_v7m_vlstm helper_v7m_vlstm_arm
 #define helper_v8m_stackcheck helper_v8m_stackcheck_arm
 #define helper_vfp_absd helper_vfp_absd_arm

qemu/armeb.h

@@ -1749,6 +1749,7 @@
 #define helper_v7m_mrs helper_v7m_mrs_armeb
 #define helper_v7m_msr helper_v7m_msr_armeb
 #define helper_v7m_tt helper_v7m_tt_armeb
+#define helper_v7m_vlldm helper_v7m_vlldm_armeb
 #define helper_v7m_vlstm helper_v7m_vlstm_armeb
 #define helper_v8m_stackcheck helper_v8m_stackcheck_armeb
 #define helper_vfp_absd helper_vfp_absd_armeb

qemu/header_gen.py

@@ -1755,6 +1755,7 @@ symbols = (
     'helper_v7m_mrs',
     'helper_v7m_msr',
     'helper_v7m_tt',
+    'helper_v7m_vlldm',
     'helper_v7m_vlstm',
     'helper_v8m_stackcheck',
     'helper_vfp_absd',

qemu/m68k.h

@@ -1749,6 +1749,7 @@
 #define helper_v7m_mrs helper_v7m_mrs_m68k
 #define helper_v7m_msr helper_v7m_msr_m68k
 #define helper_v7m_tt helper_v7m_tt_m68k
+#define helper_v7m_vlldm helper_v7m_vlldm_m68k
 #define helper_v7m_vlstm helper_v7m_vlstm_m68k
 #define helper_v8m_stackcheck helper_v8m_stackcheck_m68k
 #define helper_vfp_absd helper_vfp_absd_m68k

qemu/mips.h

@@ -1749,6 +1749,7 @@
 #define helper_v7m_mrs helper_v7m_mrs_mips
 #define helper_v7m_msr helper_v7m_msr_mips
 #define helper_v7m_tt helper_v7m_tt_mips
+#define helper_v7m_vlldm helper_v7m_vlldm_mips
 #define helper_v7m_vlstm helper_v7m_vlstm_mips
 #define helper_v8m_stackcheck helper_v8m_stackcheck_mips
 #define helper_vfp_absd helper_vfp_absd_mips

qemu/mips64.h

@@ -1749,6 +1749,7 @@
 #define helper_v7m_mrs helper_v7m_mrs_mips64
 #define helper_v7m_msr helper_v7m_msr_mips64
 #define helper_v7m_tt helper_v7m_tt_mips64
+#define helper_v7m_vlldm helper_v7m_vlldm_mips64
 #define helper_v7m_vlstm helper_v7m_vlstm_mips64
 #define helper_v8m_stackcheck helper_v8m_stackcheck_mips64
 #define helper_vfp_absd helper_vfp_absd_mips64

qemu/mips64el.h

@@ -1749,6 +1749,7 @@
 #define helper_v7m_mrs helper_v7m_mrs_mips64el
 #define helper_v7m_msr helper_v7m_msr_mips64el
 #define helper_v7m_tt helper_v7m_tt_mips64el
+#define helper_v7m_vlldm helper_v7m_vlldm_mips64el
 #define helper_v7m_vlstm helper_v7m_vlstm_mips64el
 #define helper_v8m_stackcheck helper_v8m_stackcheck_mips64el
 #define helper_vfp_absd helper_vfp_absd_mips64el

qemu/mipsel.h

@@ -1749,6 +1749,7 @@
 #define helper_v7m_mrs helper_v7m_mrs_mipsel
 #define helper_v7m_msr helper_v7m_msr_mipsel
 #define helper_v7m_tt helper_v7m_tt_mipsel
+#define helper_v7m_vlldm helper_v7m_vlldm_mipsel
 #define helper_v7m_vlstm helper_v7m_vlstm_mipsel
 #define helper_v8m_stackcheck helper_v8m_stackcheck_mipsel
 #define helper_vfp_absd helper_vfp_absd_mipsel

qemu/powerpc.h

@@ -1749,6 +1749,7 @@
 #define helper_v7m_mrs helper_v7m_mrs_powerpc
 #define helper_v7m_msr helper_v7m_msr_powerpc
 #define helper_v7m_tt helper_v7m_tt_powerpc
+#define helper_v7m_vlldm helper_v7m_vlldm_powerpc
 #define helper_v7m_vlstm helper_v7m_vlstm_powerpc
 #define helper_v8m_stackcheck helper_v8m_stackcheck_powerpc
 #define helper_vfp_absd helper_vfp_absd_powerpc

qemu/riscv32.h

@@ -1749,6 +1749,7 @@
 #define helper_v7m_mrs helper_v7m_mrs_riscv32
 #define helper_v7m_msr helper_v7m_msr_riscv32
 #define helper_v7m_tt helper_v7m_tt_riscv32
+#define helper_v7m_vlldm helper_v7m_vlldm_riscv32
 #define helper_v7m_vlstm helper_v7m_vlstm_riscv32
 #define helper_v8m_stackcheck helper_v8m_stackcheck_riscv32
 #define helper_vfp_absd helper_vfp_absd_riscv32

qemu/riscv64.h

@@ -1749,6 +1749,7 @@
 #define helper_v7m_mrs helper_v7m_mrs_riscv64
 #define helper_v7m_msr helper_v7m_msr_riscv64
 #define helper_v7m_tt helper_v7m_tt_riscv64
+#define helper_v7m_vlldm helper_v7m_vlldm_riscv64
 #define helper_v7m_vlstm helper_v7m_vlstm_riscv64
 #define helper_v8m_stackcheck helper_v8m_stackcheck_riscv64
 #define helper_vfp_absd helper_vfp_absd_riscv64

qemu/sparc.h

@@ -1749,6 +1749,7 @@
 #define helper_v7m_mrs helper_v7m_mrs_sparc
 #define helper_v7m_msr helper_v7m_msr_sparc
 #define helper_v7m_tt helper_v7m_tt_sparc
+#define helper_v7m_vlldm helper_v7m_vlldm_sparc
 #define helper_v7m_vlstm helper_v7m_vlstm_sparc
 #define helper_v8m_stackcheck helper_v8m_stackcheck_sparc
 #define helper_vfp_absd helper_vfp_absd_sparc

qemu/sparc64.h

@@ -1749,6 +1749,7 @@
 #define helper_v7m_mrs helper_v7m_mrs_sparc64
 #define helper_v7m_msr helper_v7m_msr_sparc64
 #define helper_v7m_tt helper_v7m_tt_sparc64
+#define helper_v7m_vlldm helper_v7m_vlldm_sparc64
 #define helper_v7m_vlstm helper_v7m_vlstm_sparc64
 #define helper_v8m_stackcheck helper_v8m_stackcheck_sparc64
 #define helper_vfp_absd helper_vfp_absd_sparc64

qemu/target/arm/helper.c

@@ -7192,6 +7192,12 @@ void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr)
     g_assert_not_reached();
 }
 
+void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr)
+{
+    /* translate.c should never generate calls here in user-only mode */
+    g_assert_not_reached();
+}
+
 uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
 {
     /* The TT instructions can be used by unprivileged code, but in
@@ -8281,6 +8287,54 @@ void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr)
     env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_FPCA_MASK;
 }
 
+void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr)
+{
+    /* fptr is the value of Rn, the frame pointer we load the FP regs from */
+    assert(env->v7m.secure);
+
+    if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)) {
+        return;
+    }
+
+    /* Check access to the coprocessor is permitted */
+    if (!v7m_cpacr_pass(env, true, arm_current_el(env) != 0)) {
+        raise_exception_ra(env, EXCP_NOCP, 0, 1, GETPC());
+    }
+
+    if (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_LSPACT_MASK) {
+        /* State in FP is still valid */
+        env->v7m.fpccr[M_REG_S] &= ~R_V7M_FPCCR_LSPACT_MASK;
+    } else {
+        bool ts = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MASK;
+        int i;
+        uint32_t fpscr;
+
+        if (fptr & 7) {
+            raise_exception_ra(env, EXCP_UNALIGNED, 0, 1, GETPC());
+        }
+
+        for (i = 0; i < (ts ? 32 : 16); i += 2) {
+            uint32_t slo, shi;
+            uint64_t dn;
+            uint32_t faddr = fptr + 4 * i;
+
+            if (i >= 16) {
+                faddr += 8; /* skip the slot for the FPSCR */
+            }
+
+            slo = cpu_ldl_data(env, faddr);
+            shi = cpu_ldl_data(env, faddr + 4);
+
+            dn = (uint64_t) shi << 32 | slo;
+            *aa32_vfp_dreg(env, i / 2) = dn;
+        }
+        fpscr = cpu_ldl_data(env, fptr + 0x40);
+        vfp_set_fpscr(env, fpscr);
+    }
+
+    env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK;
+}
+
 static bool v7m_push_stack(ARMCPU *cpu)
 {
     /* Do the "set up stack frame" part of exception entry,

qemu/target/arm/helper.h

@@ -74,6 +74,7 @@ DEF_HELPER_3(v7m_tt, i32, env, i32, i32)
 DEF_HELPER_1(v7m_preserve_fp_state, void, env)
 
 DEF_HELPER_2(v7m_vlstm, void, env, i32)
+DEF_HELPER_2(v7m_vlldm, void, env, i32)
 
 DEF_HELPER_2(v8m_stackcheck, void, env, i32)
 

qemu/target/arm/translate.c

@@ -12001,7 +12001,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
                     TCGv_i32 fptr = load_reg(s, rn);
 
                     if (extract32(insn, 20, 1)) {
-                        /* VLLDM */
+                        gen_helper_v7m_vlldm(tcg_ctx, tcg_ctx->cpu_env, fptr);
                     } else {
                         gen_helper_v7m_vlstm(tcg_ctx, tcg_ctx->cpu_env, fptr);
                     }

qemu/x86_64.h

@@ -1749,6 +1749,7 @@
 #define helper_v7m_mrs helper_v7m_mrs_x86_64
 #define helper_v7m_msr helper_v7m_msr_x86_64
 #define helper_v7m_tt helper_v7m_tt_x86_64
+#define helper_v7m_vlldm helper_v7m_vlldm_x86_64
 #define helper_v7m_vlstm helper_v7m_vlstm_x86_64
 #define helper_v8m_stackcheck helper_v8m_stackcheck_x86_64
 #define helper_vfp_absd helper_vfp_absd_x86_64