yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-08-03 23:41:16 +00:00
Code Issues Packages Projects Releases Wiki Activity

fpu/softfloat: Pass FloatClass to pickNaNMulAdd

Browse source 
For each operand, pass a single enumeration instead of a pair of booleans.
The commit also merges multiple different ifdef-selected implementations
of pickNaNMulAdd into a single function whose body is ifdef-selected.

Backports commit 3bd2dec1a1e8fadb49e3ff2e2633f79e01a25c41 from qemu
This commit is contained in:
Richard Henderson 2018-05-19 23:58:58 -04:00 committed by Lioncash
parent d03c570049
commit 77bee9e8a5
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 28 additions and 46 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

69
qemu/fpu/softfloat-specialize.h
View file

@ -594,15 +594,14 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
| information. | information.
| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN | Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
*----------------------------------------------------------------------------*/ *----------------------------------------------------------------------------*/
#if defined(TARGET_ARM) static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, bool infzero, float_status *status)
flag cIsQNaN, flag cIsSNaN, flag infzero,
float_status *status)
{ {
#if defined(TARGET_ARM)
/* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
* the default NaN * the default NaN
*/ */
if (infzero && cIsQNaN) { if (infzero && is_qnan(c_cls)) {
float_raise(float_flag_invalid, status); float_raise(float_flag_invalid, status);
return 3; return 3;
} }
@ -610,25 +609,20 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
/* This looks different from the ARM ARM pseudocode, because the ARM ARM /* This looks different from the ARM ARM pseudocode, because the ARM ARM
* puts the operands to a fused mac operation (a*b)+c in the order c,a,b. * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
*/ */
if (cIsSNaN) { if (is_snan(c_cls)) {
return 2; return 2;
} else if (aIsSNaN) { } else if (is_snan(a_cls)) {
return 0; return 0;
} else if (bIsSNaN) { } else if (is_snan(b_cls)) {
return 1; return 1;
} else if (cIsQNaN) { } else if (is_qnan(c_cls)) {
return 2; return 2;
} else if (aIsQNaN) { } else if (is_qnan(a_cls)) {
return 0; return 0;
} else { } else {
return 1; return 1;
} }
}
#elif defined(TARGET_MIPS) #elif defined(TARGET_MIPS)
static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
flag cIsQNaN, flag cIsSNaN, flag infzero,
float_status *status)
{
/* For MIPS, the (inf,zero,qnan) case sets InvalidOp and returns /* For MIPS, the (inf,zero,qnan) case sets InvalidOp and returns
* the default NaN * the default NaN
*/ */
@ -639,41 +633,36 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
if (snan_bit_is_one(status)) { if (snan_bit_is_one(status)) {
/* Prefer sNaN over qNaN, in the a, b, c order. */ /* Prefer sNaN over qNaN, in the a, b, c order. */
if (aIsSNaN) { if (is_snan(a_cls)) {
return 0; return 0;
} else if (bIsSNaN) { } else if (is_snan(b_cls)) {
return 1; return 1;
} else if (cIsSNaN) { } else if (is_snan(c_cls)) {
return 2; return 2;
} else if (aIsQNaN) { } else if (is_qnan(a_cls)) {
return 0; return 0;
} else if (bIsQNaN) { } else if (is_qnan(b_cls)) {
return 1; return 1;
} else { } else {
return 2; return 2;
} }
} else { } else {
/* Prefer sNaN over qNaN, in the c, a, b order. */ /* Prefer sNaN over qNaN, in the c, a, b order. */
if (cIsSNaN) { if (is_snan(c_cls)) {
return 2; return 2;
} else if (aIsSNaN) { } else if (is_snan(a_cls)) {
return 0; return 0;
} else if (bIsSNaN) { } else if (is_snan(b_cls)) {
return 1; return 1;
} else if (cIsQNaN) { } else if (is_qnan(c_cls)) {
return 2; return 2;
} else if (aIsQNaN) { } else if (is_qnan(a_cls)) {
return 0; return 0;
} else { } else {
return 1; return 1;
} }
} }
}
#elif defined(TARGET_PPC) #elif defined(TARGET_PPC)
static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
flag cIsQNaN, flag cIsSNaN, flag infzero,
float_status *status)
{
/* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
* to return an input NaN if we have one (ie c) rather than generating * to return an input NaN if we have one (ie c) rather than generating
* a default NaN * a default NaN
@ -686,31 +675,27 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
/* If fRA is a NaN return it; otherwise if fRB is a NaN return it; /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
* otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
*/ */
if (aIsSNaN || aIsQNaN) { if (is_nan(a_cls)) {
return 0; return 0;
} else if (cIsSNaN || cIsQNaN) { } else if (is_nan(c_cls)) {
return 2; return 2;
} else { } else {
return 1; return 1;
} }
} }
#else #else
/* A default implementation: prefer a to b to c. /* A default implementation: prefer a to b to c.
* This is unlikely to actually match any real implementation. * This is unlikely to actually match any real implementation.
*/ */
static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, if (is_nan(a_cls)) {
flag cIsQNaN, flag cIsSNaN, flag infzero,
float_status *status)
{
if (aIsSNaN || aIsQNaN) {
return 0; return 0;
} else if (bIsSNaN || bIsQNaN) { } else if (is_nan(b_cls)) {
return 1; return 1;
} else { } else {
return 2; return 2;
} }
}
#endif #endif
}
/*---------------------------------------------------------------------------- /*----------------------------------------------------------------------------
| Takes two single-precision floating-point values `a' and `b', one of which | Takes two single-precision floating-point values `a' and `b', one of which

5
qemu/fpu/softfloat.c
View file

@ -602,10 +602,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatParts b, FloatParts c,
s->float_exception_flags |= float_flag_invalid; s->float_exception_flags |= float_flag_invalid;
} }
which = pickNaNMulAdd(is_qnan(a.cls), is_snan(a.cls), which = pickNaNMulAdd(a.cls, b.cls, c.cls, inf_zero, s);
is_qnan(b.cls), is_snan(b.cls),
is_qnan(c.cls), is_snan(c.cls),
inf_zero, s);
if (s->default_nan_mode) { if (s->default_nan_mode) {
/* Note that this check is after pickNaNMulAdd so that function /* Note that this check is after pickNaNMulAdd so that function