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target/mips: Style improvements in cp0_timer.c
Fixes mostly errors and warnings reported by 'checkpatch.pl -f'. Backports commit 2f0d0196721d207297ce00a6cb39fc52005ccc7a from qemu
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8767d64b66
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780b748780
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@ -29,7 +29,7 @@
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#define TIMER_FREQ 100 * 1000 * 1000
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/* XXX: do not use a global */
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uint32_t cpu_mips_get_random (CPUMIPSState *env)
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uint32_t cpu_mips_get_random(CPUMIPSState *env)
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{
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static uint32_t lfsr = 1;
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static uint32_t prev_idx = 0;
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@ -70,7 +70,7 @@ static void cpu_mips_timer_expire(CPUMIPSState *env)
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}
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#endif
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uint32_t cpu_mips_get_count (CPUMIPSState *env)
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uint32_t cpu_mips_get_count(CPUMIPSState *env)
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{
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if (env->CP0_Cause & (1 << CP0Ca_DC)) {
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return env->CP0_Count;
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@ -89,7 +89,7 @@ uint32_t cpu_mips_get_count (CPUMIPSState *env)
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}
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}
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void cpu_mips_store_count (CPUMIPSState *env, uint32_t count)
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void cpu_mips_store_count(CPUMIPSState *env, uint32_t count)
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{
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#if 0
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/*
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@ -97,9 +97,9 @@ void cpu_mips_store_count (CPUMIPSState *env, uint32_t count)
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* So env->timer may be NULL, which is also the case with KVM enabled so
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* treat timer as disabled in that case.
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*/
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if (env->CP0_Cause & (1 << CP0Ca_DC) || !env->timer)
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if (env->CP0_Cause & (1 << CP0Ca_DC) || !env->timer) {
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env->CP0_Count = count;
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else {
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} else {
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/* Store new count register */
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env->CP0_Count =
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count - (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
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@ -110,13 +110,15 @@ void cpu_mips_store_count (CPUMIPSState *env, uint32_t count)
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#endif
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}
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void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value)
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void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value)
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{
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env->CP0_Compare = value;
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if (!(env->CP0_Cause & (1 << CP0Ca_DC)))
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if (!(env->CP0_Cause & (1 << CP0Ca_DC))) {
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cpu_mips_timer_update(env);
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if (env->insn_flags & ISA_MIPS32R2)
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}
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if (env->insn_flags & ISA_MIPS32R2) {
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env->CP0_Cause &= ~(1 << CP0Ca_TI);
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}
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//qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
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}
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